Universal Serial Bus OTG Controller
UG0331 User Guide Revision 15.0
337
10.3.9
ULPI and Configuration Registers
These registers correspond to the ULPI interface and link specific. This section covers all registers in this
category along with the address offset, functionality, and per bit details.
Table 252 •
ULPI and Configuration Registers
Register Name
Address
Width
R/W
Type
Reset
Value
Description
ULPI_VBUS_CTRL_REG
(0x40043070)
0x40043070 8
R
0
ULPI PHYs can use an external charge pump to
generate VBus rather than an internal charge
pump. This register allows selection of the
external charge pump. It also allows this
selection to be displayed through an external
VBus indicator.
This register is read back from the PHY clock
domain. These bits do not therefore return
updated values while the PHY is suspended.
ULPI_CARKIT_CTRL_REG
(0x40043071)
0x40043071 8
R
0
Provides the basic control needed by ULPI-
compatible PHYs when interfacing to in-car
CarKit systems.
ULPI_IRQ_MASK_REG
(0x40043072)
0x40043072 8
R
0
Enables the assertion of MC_NINT in response
to the possible interrupt sources.
0x40043073 8
R
0
This register shows the unmasked value of the
possible interrupt sources.
0x40043074 8
R
0
Contains the data associated with register
reads/writes conducted through the ULPI
interface.
0x40043075 8
R
0
Contains the address of the register being
read/written through the ULPI interface.
0x40043076 8
R
0
Contains control and status bits relating to the
register being read/written through the ULPI
interface.
ULPI_RAW_DATA_REG
(0x40043077)
(Asynchronous)
ULPI_RAW_DATA_REG
(0x40043077)
(Synchronous)
0x40043077 8
R
0
This register is used in Asynchronous modes to
sample the ULPI bus and in Synchronous mode
to store the last received command.
0x40043078 8
R
0
Allows read-back of the number of transmit and
receive endpoints included in the design.
0x40043079 8
R
0
Provides information about the number of DMA
channels and the width of the RAM.
0x4004307A 8
RW
0x5C
Allows configuration of link-specific delays
0x4004307B 8
RW
0x3C
This register allows setting duration of the Vbus
pulsing charge
0x4004307C 8
RW
0x80
Sets the minimum time gap that is to be allowed
between the start of the last transaction and the
EOF for high speed transactions.
Содержание SmartFusion2 MSS
Страница 1: ...UG0331 User Guide SmartFusion2 Microcontroller Subsystem ...
Страница 166: ...Cortex M3 Processor Reference Material UG0331 User Guide Revision 15 0 132 ...
Страница 200: ...Embedded NVM eNVM Controllers UG0331 User Guide Revision 15 0 166 Figure 87 System Builder Window ...
Страница 407: ...Universal Serial Bus OTG Controller UG0331 User Guide Revision 15 0 373 ...
Страница 806: ...Fabric Interface Controller UG0331 User Guide Revision 15 0 772 Figure 345 FIC Master AHB Lite Subsystem ...