Universal Serial Bus OTG Controller
UG0331 User Guide Revision 15.0
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10.2.1.5 UTM Synchronization
The role of the UTM synchronize block is to synchronize between the transceiver macrocell 60 MHz
clock domain and the SmartFusion2 USB OTG controller's system clock. This allows the rest of the USB
OTG controller to run at the desired system clock. This block also performs the high speed detection
handshaking and handles the host negotiation protocol (HNP) and the session request protocol of the
OTG specification in point-to-point communications with another USB OTG device.
10.2.1.6 PHY Interfaces
The USB controller supports both universal transceiver macrocell interface plus (UTMI+) and universal
low pin count interface (ULPI) at the link side. For ULPI interface I/Os are routed through the MSS onto
multi standard I/Os (MSIOs) and for UTMI, I/Os are routed through the FPGA fabric. The built-in
multiplexer (MUX) and de-multiplexer (DeMUX) logic allows the selection of UTMI or ULPI through the
Libero SoC software.
Note:
The SmartFusion2 devices support OTG PHY but do not support the TI NON-OTG PHY.
10.2.2
USB OTG Controller Interface Signals
This section describes the ULPI and UTMI+ fabric interfaces.
10.2.2.1 ULPI (UTMI+ Low Pin Interface) I/O Interface
The SmartFusion2 USB OTG controller communicates with the external ULPI PHY device using this
interface. As shown in the following figure, the ULPI interface is routed through the MSIO ports. These
I/Os are dedicated to the USB ULPI interface only. When the USB OTG controller is selected during
configuration, these I/Os are not multiplexed with other peripherals.
For interfacing with ULPI PHY, the USB MSIO signals are connected to four separate mutually exclusive
I/O groups: USBA, USBB, USBC, and USBD I/O groups. In M2S050 devices, only the USBD I/O group is
available; whereas in the M2S025 and M2S010, only the USBA, USBB, and USBC I/O groups are
available.
Table 190 •
ULPI Interface Signals at SmartFusion2 External I/Os
Signal Name
Direction Description
ULPI_DATA[7:0] In/Out
ULPI input data bus to ULPI link wrapper
ULPI_DIR
In
Controls the direction of the data bus. The PHY must drive this signal high when it has
the data to be transferred. Otherwise, the PHY should drive this signal low.
ULPI_STP
Out
Data end control, driven high for one XCLK cycle to indicate the end of a transmit
operation. It can also be used to stop the current receive operation.
Asynchronous path from DIR.
ULPI_NXT
In
Data control, driven high by the PHY to throttle all data types except the interrupt data
and the results of register reads.
ULPI_XCLK
In
Transceiver macrocell clock; 60 MHz
Содержание SmartFusion2 MSS
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