Hardware Components
UG0048 User Guide Revision 5.1
10
3.5.3.1
Test Points
All test points on the board are fitted with small test loops. These test points are labeled on the silkscreen
as TP1, TP2, and so on. All such test points are also labeled on the silk screen with the voltage expected
to be observed at that test point. Voltages will be one of 3.3 V, 2.5 V, 1.8 V, 1.5 V, or GND. When
measuring the voltage at a test point with a DVM (digital voltage multimeter), the ground lead must be
connected to a test point labeled GND and the voltage lead must be connected to the voltage to be
tested. All voltage labels on the board are relative to a 0 V ground reference or GND.
3.5.3.2
Prototyping Area
The prototyping area to the right of the board has the bottom two rows of pins connected to ground,
labeled as GND on the silk screen and enclosed in a box, giving 16 holes connected to 0 V. The top two
rows of pins are connected to various power supply rails internally in the board.
They are grouped into squares of four pins from left to right as follows: 3.3 V, 2.5 V, 1.8 V, and 1.5 V,
giving four holes for each voltage level. All other holes in the prototyping area are unconnected and may
be used to hold various discrete components as necessary for experimentation.
Next to the prototyping area is U2, which is a space for an optional oscillator. This space may be used for
fitting a second oscillator to the board, similar to the one used at U1, so as to provide two different
frequency clocks to the FPGA.
On the reverse side of the board, there is an area labeled U5, which is a TQ100 pattern with some
surrounding pads. This area is used to solder a TQ100 part, and then connect that part by adding
discrete wires to the pads and connecting it to desired pins on the board. The main purpose of this is to
allow a previously programmed TQ100 packaged device to be used to provide a more interesting system
application.
3.5.3.3
Layering on Board
The complete board design and manufacturing files are available at:
The board file is in allegro format, which allows an end user to create the appropriate Gerbers and other
board views as needed.
The board is fabricated with 6 layers of copper. The layers are arranged as follows from the top of the
board down to the bottom:
Layer 1: Top signal layer
Layer 2: Ground plane
Layer 3: Signal layer 3, used for LVDS receive and other signals
Layer 4: Signal layer 4, used for LVDS transmit and other signals
Layer 5: Power plane
Layer 6: Bottom signal layer
Note:
For signal integrity that the two LVDS layers are sandwiched between ground and power planes to
isolate them as best as possible from external influences.
3.6
Clock Circuits
The ProASIC3/E Starter Kit board has two clock circuits: a 40 MHz oscillator and a manual clock.
3.6.1
40 MHz Oscillator
The 40 MHz oscillator on the board is a 10 ppm stability crystal module which gives good LVDS
performance. For better stability, an external oscillator is provided through the SMA connector. Typically,
a TCXO gives 1 ppm stability and an OCXO gives 0.1 ppm stability. Both the default on-board oscillator
and the SMA are connected to the CLK F input of the west bank of the FPGA. Position is also provided
on the board for mounting a second crystal oscillator module connected to the CLK C input of the FPGA
on the east bank.
Содержание ProASIC3/E Proto Kit
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