PolarFire MPF300T FPGA Video Kit
50200872 UG0872 User Guide Revision 1.0
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4
Board Components and Operations
This section describes the key components of the PolarFire Video board and important board
operations.
4.1
Memory Interface
The following figure shows the memory interface scheme.
Figure 4 • Memory Interface
As shown in the preceding figure, Four 4 Gb DDR4 SDRAM chips are used as flexible volatile memory for
user applications. The DDR4 interface is implemented in the HSIO Bank 0 and Bank 7.
The DDR4 SDRAM specifications are as follows:
MT40A256M16GE-083E:B
Quantity: Four chips are connected in Fly-by topology
Density: 16 Gb
Data rate: DDR4 64-bit at 166 MHz clock rate
The PolarFire video board design uses the DDR4 and POD12 standards for the DDR4 interface. The
default board assembly for the DDR4 standard uses RC terminations.
4.2
SPI Serial Flash
The following figure shows the SPI Flash and its interface with the PolarFire device.
