dsPIC33/PIC24 Family Reference Manual
DS30009711C-page 4
2006-2019 Microchip Technology Inc.
Figure 2-1:
Example of Unintended I/O Behavior
2.3
LAT Registers
The LATx register associated with an I/O pin eliminates the problems that could occur with Read-
Modify-Write instructions. A read of the LATx register returns the values held in the port output
latches instead of the values on the I/O pins. A Read-Modify-Write operation on the LATx register,
associated with an I/O port, avoids the possibility of writing the input pin values into the port
latches. A write to the LATx register has the same effect as a write to the PORTx register.
The differences between the PORTx and LATx registers can be summarized as follows:
• A write to the PORTx register writes the data value to the port latch.
• A write to the LATx register writes the data value to the port latch.
• A read of the PORTx register reads the data value on the I/O pin.
• A read of the LATx register reads the data value held in the port latch.
Any bit and its associated data and control registers that are not valid for a particular device will
be disabled. That means the corresponding LATx and TRISx registers, and the port pin, will read
as zeros.
2.4
ODC Registers
Each I/O pin can be individually configured for either normal digital output or open-drain output.
This is controlled by the PORTx Open-Drain Control register, ODCx, associated with each I/O
pin. If the ODC bit for an I/O pin is ‘
1
’, then the pin acts as an open-drain output. If the ODC bit
for an I/O pin is ‘
0
’, then the pin is configured for a normal digital output (ODC bit is valid only for
output pins). After a Reset, the status of all the bits of the ODCx register is set to ‘
0
’.
The open-drain feature allows a load to be connected to a voltage higher/lower than V
DD
on any
desired digital only pins by using external pull-up resistors. The maximum open-drain voltage
allowed is the same as the maximum V
IH
specification and the minimum is V
SS
. The ODCx reg-
ister setting takes effect in all the I/O modes, allowing the output to behave as an open-drain,
even if a peripheral is controlling the pin. Although the user could achieve the same effect by
manipulating the corresponding LAT and TRIS bits, this procedure will not allow the peripheral to
operate in Open-Drain mode (except for the default operation of the I
2
C pins). Since I
2
C pins are
already open-drain pins, the ODCx settings do not affect the I
2
C pins. Also, the ODCx settings
do not affect the JTAG output characteristics as the JTAG scan cells are inserted between the
ODCx logic and the I/O.
Example Code:
BSET
PORTA, #0
; Set pin 0 on Port A to ‘1’
BSET
PORTA, #1
; Set pin 1 on Port A to ‘1’
I/O Pin 1 Voltage
I/O Pin 0 Voltage
BSET PORTA, #0
instruction
has finished execution. Voltage
on I/O Pin 0 is starting to rise.
1
2
3
4
BSET PORTA, #1
instruction
starts execution and reads PORTA
register (bit 0 is read as ‘
0
’).
I/O Pin 0 transitions from
‘
0
’ to ‘
1
’.
BSET PORTA, #1
instruction
has finished execution. Voltage
is starting to rise on I/O Pin 1
and fall on I/O Pin 0.
Note:
Please note that the maximum V
IH
spec for the PIC24FXXKXXXX family is limited
to V
DD
. This limits open-drain capability for higher voltage generation, though it can
still be connected to lower voltage than V
DD
.