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Register Description
IF2008/PCIe / IF2008E
10.3
Set- / Reset- / Latch Register
Base addr.. + 02h (write access)
Bit
Function
0
Delete counter 1
1
Load counter 1
2
Latch counter 1
3
Reference counter 1
4
Delete counter 2
5
Load counter 2
6
Latch counter 2
7
Reference counter 2
8
Start ADC1 conversion
9
Start ADC2 conversion
10
Delete FIFO
11 to 15
Reserved
Fig. 17: Set- / Reset- / Latch register
i
By means of the bits 0 to 2 and 4 to 6, the counters can be either deleted or loaded independently of
the counter control register by the software, (addr. 14h and addr. 16h). Furthermore, the counter rea-
ding can be transferred into the latch register.
If a counter latch or load function, which should only operate in connection with a reference marker
signal is settled by the counter control register (addr. 14h and addr. 16h); this is subject to approval by
setting bit 3 or bit 7. On setting bit 3 or bit 7 the status bits 0 and 1 or 2 and 3 are reset.
All bits only need to be set, resetting them is not necessary.
After power interruption, all bits are set to “0”.
Содержание IF2008/PCIe
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