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Register Description
IF2008/PCIe / IF2008E
10.2
Fifo Data
Base addr. + 00h (read access)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C7
C6
C5
C4
C3
C2
C1
C0
D7
D6
D5
D4
D3
D2
D1
D0
Code bits
Data bits
Fig. 15: FIFO data memory
Bit 0 to 7
Include the data buffered
Bit 7 to 15
Mark the data code
Code bits
Bytes 0 to 7
Channel 0 to 7
Data source 0 to 3
C7
C6
C5
C4
C3
C2
C1
C0
C7
C6
Daten source
0
0
Sensor
0
1
Encoder
1
0
Switching input (IN 1 ... 4 > channel 0, RxD 1 ... 6 > channel 1)
1
1
ADC
Fig. 16: FIFO data memory - data sources
Содержание IF2008/PCIe
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