Measurement Computing Data Translation DT3010 Series, Руководство пользователя, Страница: 127 / 232

Chapter 6
126
To stop a continuously-paced analog output operation, you can stop sending data to the
board, letting the board stop when it runs out of data, or you can perform either an
orderly stop or an abrupt stop using software. In an orderly stop, the board finishes
outputting the specified number of samples, then stops; all subsequent triggers are
ignored. In an abrupt stop, the board stops outputting samples immediately; all
subsequent triggers are ignored.
Continuously-Paced Analog Output
Use continuously-paced analog output mode if you want to accurately control the period
between conversions of individual analog output channels in the analog output channel list.
The host computer transfers digital values to write to the DACs from allocated circular buffers
in computer memory to the output FIFO on the board. DT3010, DT3010-268, and DT3016
boards have a 4 kSample output FIFO; DT3010/32 and DT3010/32-268 boards have a 32
kSample output FIFO for demanding analog output operations. Use software to allocate the
number of buffers and to specify the values. It is recommended that you allocate a minimum
of two buffers.
When it detects a trigger, the board outputs the values in the output FIFO to the DACs at the
same time. Even samples (0, 2, 4, and so on) are written to entry 0 in the channel list; odd
samples (1, 3, 5, and so on) are written to entry 1 in the channel list. The operation repeats
continuously until no more buffers are on the subsystem queue or you stop the operation.
Refer to
page 127 for more information on buffers.
Ensure that the host computer transfers data to the output FIFO fast enough so that the output
FIFO does not empty completely; otherwise, an output FIFO underrun error results. Note that
the output FIFO counter increments each time the host loads a value into the output FIFO and
decrements each time the DAC reads a value from the output FIFO; the counter is reset to 0
when the output FIFO is reset. To avoid the output FIFO underrun error in
continuously-paced mode, the host computer can read the output FIFO counter to determine
how many samples remain in the output FIFO, and transfer more data before the output FIFO
empties.
The conversion rate is determined by the frequency of the D/A output clock. For DT3010,
DT3010-268, DT3010/32, and DT3010/32-268 boards, the maximum throughput rate in this
mode is 500 kHz (500 kSamples/s) in 100 mV steps or 200 kHz (200 kSamples/s) in full-scale
steps. For DT3016 boards, the maximum throughput rate in this mode is 200 kHz
(200 kSamples/s) in 100 mV steps or 100 kHz (100 kSamples/s) in full-scale steps. Note that
rate is system-dependent. Refer to
page 123 for more information on the D/A output clock.
To select continuously-paced analog output mode, use software to specify the following
parameters:
• Set the dataflow as Continuous.
• Set WrapSingleBuffer to False to use multiple buffers. A minimum of two buffers is
recommended.
• Set the trigger source as any of the supported trigger sources. Refer to page 124 for more
information on the supported trigger sources.