49
RCVFIFO Register
Meaning:
Receive FIFO.
Mode:
Host only
As a peripheral sends data over the bus in response to a host IN request, the SIE fills an internal
FIFO with data. The CPU reads bytes from the FIFO by repeatedly reading the RCVFIFO
register.
The CPU should never write the RCVFIFO, because it would corrupt the received data.
Programming Notes
After an error-free data packet arrives, the SIE loads the RCVBC register with the number of
received bytes and asserts the RCVDAVIRQ bit (Receive Data Available IRQ). The CPU
responds first by reading the RCVBC register to determine the number of bytes in the RCVFIFO,
clearing the RCVDAVIRQ bit, and finally reading the bytes with repeated reads to the
RCVFIFO register.
The RCVFIFO register connects to two internal 64-byte FIFOs. The two FIFOs allow the SIE to
load IN data transmitted by a peripheral into one FIFO, while the CPU concurrently empties the
other FIFO. If the CPU clears the RCVDAVIRQ bit when there is another packet waiting in the
other FIFO, the SIE immediately re-asserts the RCVDAVIRQ bit.
The CPU should read RCVFIFO bytes only when USB received data is available, indicated by
RCVDAVIRQ = 1.