Maxim Integrated MAX32660, Руководство пользователя

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MAX32660 User Guide
Maxim Integrated Page 89 of 195
UART Control 0 Register UARTn_CTRL0 [0x0000]
Bits Name Access Reset Description
6 rxflush R/W1O 0
Receive FIFO Flush
Write 1 to flush the receive FIFO
Cleared to 0 by hardware when flush is completed
5 txflush R/W1O 0
Transmit FIFO Flush
Write 1 to flush the Transmit FIFO
Cleared to 0 by hardware when flush is completed
4 parity_lvl R/W 0
Parity Level Select
0: Parity is based on number of 0 bits in the character.
1: Parity is based on number of 1 bits in the character.
3:2 parity_mode R/W 0
Parity Mode Select
0: Even parity
1: Odd Parity
2: Mark parity
3: Space parity
1 parity_en R/W 0
Parity Enable
0: No parity
1: Parity enabled as c1 bit
0 enable R/W 0
UART Enable
0: UART disabled. FIFOs are flushed, bit rate generator is off.
1: UART Enabled, bit rate generator is active.
Table 8-4: UART Control 1 Register
UART Control 1 Register UARTn_CTRL1 [0x0004]
Bits Name Access Reset Description
31:22 0 R/W 0
Reserved for Future Use
Do not modify this field.
21:16 rts_fifo_lvl R/W 0
RTS RX FIFO Threshold Level
When the RX FIFO level is equal to or greater than this level, assert RTS output signal
to inform the transmitting UART to stop sending data to this UART.
Valid values are from 0 to 32.
15:14 - R/W 0
Reserved for Future Use
Do not modify this field.
13:8 tx_fifo_lvl R/W 0
TX FIFO Threshold Level
When the TX FIFO level is less than or equal to this level the UARTn_INT_FL .tx_fifo_lvl
interrupt flag is set.
Valid values are from 0 to 32.
7:6 - R/W 0
Reserved for Future Use
Do not modify this field.
5:0 rx_fifo_lvl R/W 0
RX FIFO Threshold Level
When the RX FIFO reaches this level or higher the UARTn_INT_FL .rx_fifo_lvl interrupt
flag is set.
Valid values are from 0 to 32.