Maxim Integrated MAX32660, Руководство пользователя

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MAX32660 User Guide
Maxim Integrated Page 82 of 195
Table 7-13: DMA Source Register
DMA Source Register DMAn_SRC [0x0108]
Bits Name Access Reset Description
31:0 src R/W 0 Source Device Address
For peripheral transfers, the actual address field is either ignored or forced to zero
because peripherals only have one location to read/write data based on the request
select chosen.
If DMAn_CFG .srcinc = 1:
•
This register is incremented on each AHB transfer cycle by one, two, or four bytes
depending on the data width.
If DMAn_CFG .srcinc = 0:
•
This register remains constant.
If a CTZ condition occurs while DMAn_CFG .rlden = 1, then this register is reloaded
with the contents of the DMAn_SRC_RLD register.
Table 7-14: DMA Destination Register
DMA Destination Register DMAn_DST [0x010C]
Bits Name Access Reset Description
31:0 dst R/W 0 Destination Device Address
For peripheral transfers, the actual address field is either ignored or forced to zero
because peripherals only have one location to read/write data based on the request
select chosen.
If DMAn_CFG .dstinc = 1, then this register is incremented on every AHB transfer cycle
by one, two, or four bytes depending on the data width.
If a CTZ condition occurs while DMAn_CFG .rlden = 1, then this register is reloaded
with the contents of the DMAn_DST_RLD register.
Table 7-15: DMA Count Register
DMA Count Register DMAn_CNT [0x0110]
Bits Name Access Reset Description
31:24 - RO 0 Reserved for Future Use
Do not modify this field.
23:0 cnt R/W 0 DMA Counter
Load this register with the number of bytes to transfer.
This counter decreases on every AHB access to DMA FIFO. The decrement is one, two,
or four bytes depending on the data width.
When the counter reaches 0, a CTZ condition is triggered.
If a CTZ condition occurs while DMAn_CFG .rlden = 1, then this register is reloaded with
the contents of the DMAn_CNT_RLD register.
0x000000: 0 Byte
0x000001: 1 Byte
0x000002: 2 Bytes
…
0xFFFFFF:16,777,215 Bytes