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MAX32600 User’s Guide
Analog Front End
8.3 ADC
Field
Bits
Default
Access
Description
adc_smp_ext
11
0
R/W
Reserved Field - Do Not Modify
This field should not be modified by the user. For proper operation, this field must be left at its default value.
ADC_CTRL0.adc_clk_en
Field
Bits
Default
Access
Description
adc_clk_en
12
0
R/W
ADC Interface Clock Enable
• 0: ADC clock is gated off
• 1: ADC clock is enabled
This bit must be set to 1 at least 4 ADC clock cycles prior to measuring analog data.
ADC_CTRL0.cpu_adc_rst
Field
Bits
Default
Access
Description
cpu_adc_rst
13
0
R/W
CPU ADC Reset
• 0: ADC normal operation
• 1: Resets ADC and clears ADC FIFO. Puts ADC in known state. Hardware resets this bit to 0 after one ADC clock cycle.
It is recommended to use this bit to reset the ADC before the first ADC sample is measured after any system reset.
ADC_CTRL0.cpu_adc_strt
Rev.1.3 April 2015
Maxim Integrated
Page 426
Содержание MAX32600
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