Maxim Integrated MAX32600, Руководство пользователя

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MAX32600 User’s Guide Communication Peripherals 7.2 SPI
0: Interrupt source disabled; 1:Interrupt enabled.
SPIn_INTEN.tx_fifo_ae
Field Bits Default Access Description
tx_fifo_ae 4 0 R/W TXFIFO Almost Empty Int Enable
0: Interrupt source disabled; 1:Interrupt enabled.
SPIn_INTEN.rx_fifo_af
Field Bits Default Access Description
rx_fifo_af 5 0 R/W RXFIFO Almost Full Int Enable
0: Interrupt source disabled; 1:Interrupt enabled.
7.2.9.1.8 SPIn_FIFO_TRANS
Default Access Description
n/a R/W FIFO Write Space for Transaction Setup
Writes to this space result in pushes to the SPI Master Transaction FIFO. This write space supports single accesses as well as burst accesses; access widths of
8-bit, 16-bit and 32-bit are supported. Reads from this space always return zeroes.
The SPI Master Transaction FIFO is 16 bits wide and 16 levels deep. Performing a 16-bit write to this space results in a single 16-bit push to the write end of the
FIFO. A 32-bit write results in two 16-bit pushes; the least significant word is pushed first, followed by the most significant word. When two pushes occur from a single
write, a busy status will be returned by the FIFO to the AHB bus master until both pushes have completed.
If 8-bit writes are used to load the FIFO, these writes must occur in even/odd address pairs. An even byte address write will be held until the corresponding odd byte
address write is received, at which point both bytes will be pushed to the FIFO in a single 16-bit push operation (odd byte: MSB, even byte: LSB)
7.2.9.1.9 SPIn_FIFO_RSLTS
Rev.1.3 April 2015 Maxim Integrated Page 282