Maxim Integrated MAX32600, Руководство пользователя

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MAX32600 User’s Guide Peripheral Management Unit (PMU) 6.3 PMU Programming Details
RD SIZE WR SIZE Operation
00b 00b Perform 8-bit reads and 8-bit writes
00b 01b Perform 8-bit reads and pack data into 16-bit writes
00b 10b Perform 8-bit reads and pack data into 32-bit writes
01b 00b Perform 16-bit reads and unpack into 8-bit writes
01b 01b Perform 16-bit reads and writes
01b 10b Perform 16-bit reads and pack data into 32-bit writes
10b 00b Perform 32-bit reads and unpack data into 8-bit writes
10b 01b Perform 32-bit reads and unpack data into 16-bit writes
10b 10b Perform 32-bit reads and writes
XX 11 (Reserved)
11b XX (Reserved)
RD INC
• Setting this bit to 0 disables auto incrementing of the read address. This may be useful when reading from FIFO storage elements.
WR INC
• Setting this bit to 1 enables auto incrementing of the write address. This may be useful when writing to SRAM memory.
CONT
• Setting this bit to 1 allows a subsequent MOVE op code to continue operation using the read and write addresses from the previous MOVE op code.
LENGTH
• Length of transfer (in bytes) from read address to write address.
6.3.2 PMU Op Code: WRITE (0x01)
The WRITE op code will cause the write value to be written to the write address location. Only bits set in the write mask field will be modified. This allows the user to
set or clear individual bits in a 32-bit field. Write accesses may be in either the AHB or APB memory space. All accesses are restricted to 32-bit accesses. The op
code bit settings and operands are shown below.
Rev.1.3 April 2015 Maxim Integrated Page 197