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140   Appendix B: Technical information

JTAG connector

If Matrox Solios eCL/XCL has the optional Processing FPGA, the board features 
a 10-pin male JTAG connector for debugging and probing internal signals of the 
FPGA. The pin assignment, as used in JTAG mode, is as follows: 

You can connect to the JTAG connector with a standard Altera ByteBlaster II cable 
that can be purchased from the Altera Corporation. To begin debugging, you must 
first enable the connector by installing a jumper on the adjacent 2-pin connector 
(J2).

For further information on debugging with the JTAG connector, refer to the 
Quartus II documentation from the Altera Corporation. For other debugging 
information, refer to the 

Matrox Solios FPGA Developer’s Toolkit (FDK) 

manual

.

Pin

Signal

Description

1

TCK

Clock signal.

2

GND

Signal ground.

3

TDO

Data from device.

4

VCC(TRGT)

Target power supply.

5

TMS

JTAG state machine control.

6

No connect

No connect.

7

No connect

No connect.

8

No connect

No connect.

9

TDI

Data to device.

10

GND

Signal ground.

2

1

9

10

Содержание Solios eA

Страница 1: ...Matrox Solios Installation and Hardware Reference Manual no 10898 101 0400 March 27 2008...

Страница 2: ...l economic cover or consequential damages arising out of the use of or inability to use the product user documentation or related technical support including without limitation damages or costs relati...

Страница 3: ...Processing capabilities 19 On board memory 19 Additional functionality 19 Data transfer 21 Documentation conventions 21 Software 22 Essentials to get started 23 Inspecting the Matrox Solios package 24...

Страница 4: ...eA XA 39 Connecting to Matrox Solios GigE 41 Chapter 3 Using multiple Matrox Solios boards 45 Multiple board installation 46 Simultaneous image capture from different boards 46 Chapter 4 Matrox Solio...

Страница 5: ...l signals 78 Matrox Solios GigE acquisition section 86 Performance 87 Supported video sources 87 GigE Vision filter 88 Image reconstructor 88 Auxiliary I O controller 88 Processing FPGA 96 Possible pr...

Страница 6: ...nnectors on Matrox Solios eCL XCL B 126 Camera Link video input connector 127 External auxiliary I O connector 0 128 Connectors on Matrox Solios eCL XCL dual Base single Medium and eCL XCL F boards 13...

Страница 7: ...f Matrox Solios boards 163 Major revisions of Matrox Solios 164 Appendix D Acknowledgments 169 UART copyright information 170 Index Regulatory Compliance FCC Compliance Statement Industry Canada Compl...

Страница 8: ......

Страница 9: ...Chapter 1 Chapter 1 Introduction This chapter briefly describes the features of the Matrox Solios boards as well as the software that can be used with the boards...

Страница 10: ...ion with Matrox Solios eCL XCL Matrox Solios eCL XCL boards are high performance Camera Link frame grabbers and are available in three versions PCIe PCI X single Base PCIe PCI X dual Base single Mediu...

Страница 11: ...tion PSG 32 DDR up to 800 MB s 64 bit up to 528 MB s PCI X to PCI X Bridge Matrox Solios eCL XCL B Acquisition memory 32 64 128 MB MDR 26 connector ChannelLink Receiver Clock Data 24 Syncs 4 24 UART L...

Страница 12: ...receivers OptoAux 4 DB 44 and DB 9 connectors TTL buffers On a separate bracket Aux In 4 Aux Out 4 HSYNC Out 2 VSYNC Out 2 Clock Out 2 Optocoupler Aux I Os 6 ChannelLink Receiver 2 Clock Data 24 Syncs...

Страница 13: ...Ie eCL Bridge Host PCI PCI X PCIe bus LUTs 48 Demultiplexer Matrox Solios eCL XCL dual Base single Medium single Medium mode Acquisition memory 64 128 256 MB 16 Processing FPGA DDR SDRAM 64 128 256 MB...

Страница 14: ...On a separate bracket Aux In 4 Aux Out 2 HSYNC Out 1 VSYNC Out 1 Clock Out 1 Optocoupler Aux I Os 4 ChannelLink Receiver 2 Clock Data 28 Cam Ctrl 4 LVDS drivers LVDS driver receiver 16 64 DDR up to 1...

Страница 15: ...port the optional Processing FPGA PCI X to PCIe eA or PCI X to PCI X XA Bridge Input Selector 10 bit A D LUTs Clock LVDS TTL Hsync Csync LVDS TTL Vsync LVDS TTL Aux In Trigger TTL Aux Out Exposure TTL...

Страница 16: ...connectors Video to PCI X bridge Independent acquisition path VID_IN B 64 up to 800 MB s 64 bit PCI or PCI X XA up to 1 GB s On a separate bracket A Matrox Solios eA XA Dual Acquisition memory 64 128...

Страница 17: ...h 0 Independent acquisition path 1 DVI connectors 0 and 1 LVDS TTL drivers and receivers Aux In Aux In Aux Out DB 44 and DB 9 connectors Video to PCI X bridge 8 8 4 Independent acquisition path VID_IN...

Страница 18: ...100 Mbps Fast Ethernet 100BASE T and 10 Mbps Ethernet 10BASE T networks It is recommended that you use Matrox Solios GigE with Gigabit Ethernet networks to ensure maximum performance Video to PCI X B...

Страница 19: ...memory is referred to as acquisition memory Up to 256 Mbytes of additional DDR SDRAM and up to 8 Mbytes of QDRII SRAM is included if the Processing FPGA is installed This memory is referred to as ded...

Страница 20: ...os eA XA Single has one LED All Matrox Solios eCL XCL boards1 support an integrated quadrature decoder Board Auxiliary signals available Matrox Solios eCL XCL B 81 1 This is the number of auxiliary si...

Страница 21: ...er to any available Matrox display board or a third party display board in the computer Important Note that transfer of image data to a display board might require intervention from the Host CPU depen...

Страница 22: ...cognition template based and feature based and code recognition 1D 2D and composite code types MIL applications are easily ported to new Matrox hardware platforms and can be designed to take advantage...

Страница 23: ...entials to get started To begin using Matrox Solios you must have a computer with the following An available conventional PCIe PCI or PCI X slot Note that only Matrox Solios eCL eA and GigE support a...

Страница 24: ...he adapter board Note that the Matrox Solios eCL XCL B package does not aupport include an adapter board or a flat ribbon cable A supplementary 50 pin auxiliary I O mating connector The mating connect...

Страница 25: ...ectors you can use a standard cable DVI I to DVI I or DVI A to DVI A cable if the display board encodes the synchronization signals on the video data sync on green Otherwise you must use the Matrox DV...

Страница 26: ...Complete the hardware installation as described in Chapter 2 Hardware installation 2 Complete the software installation procedure described in the documentation accompanying your software package Mor...

Страница 27: ...ers registered customers additional ways of obtaining support If your question is not addressed and you are currently registered with the MIL maintenance program you can contact technical support To d...

Страница 28: ...28 Chapter 1 Introduction...

Страница 29: ...Chapter 2 Chapter 2 Hardware installation This chapter explains how to install your Matrox Solios board in your computer...

Страница 30: ...lled before you install your software 1 Remove the cover from your computer refer to your computer s documentation for instructions 2 Check that you have an empty PCIe slot in which to install your Ma...

Страница 31: ...computer s chassis Since Matrox Solios eA XA s adapter board is longer it has a support tab that can be removed if a PCI PCI X slot is selected the tab will fit into the slot s connector ensuring that...

Страница 32: ...ing the board Some x16 PCIe slots have a connector with a retainer Matrox Solios boards must not come into contact with the latch of this retainer The PCIe specification does not define appropriate ke...

Страница 33: ...rd bracket later in this chapter 7 Attach your video sources as described in the section Connecting video sources later in this chapter 8 Turn on your computer When you boot your computer Windows Plug...

Страница 34: ...other components in the computer The tab was added so that if used in a PCI PCI X slot the board would have extra support and be more sturdy To break off the tab use a set of pliers there is a groove...

Страница 35: ...uld hear a snap when the hooks of the cable s connector latch onto the internal auxiliary I O connector 4 For the adapter boards of Matrox Solios eCL XCL and eA XA connect the other end of the flat ri...

Страница 36: ...tor and then press the board firmly but carefully into the slot s connector For other types of slots or when installing the adapter board of Matrox Solios eCL XCL or the adapter bracket of Matrox Soli...

Страница 37: ...ource and the frame grabber External I O connector 0 DB 15 or DB 9 Used to transmit timing and synchronization signals and transmit receive auxiliary signals Use a standard Camera Link cable or a stan...

Страница 38: ...nsmit timing and synchronization signals and transmit receive auxiliary signals The connector is located on the edge of the board making the signals accessible from inside the computer enclosure To ac...

Страница 39: ...on and communication signals between the video source and the frame grabber For Matrox Solios eA XA Quad you can connect up to 4 video sources to each connector Connector 0 provides source A for acqui...

Страница 40: ...open ended wires on the other end the open ended wires allow you to connect to some timing synchronization and control signals of the frame grabber Two of these cables are required to connect to more...

Страница 41: ...s and transmit receive auxiliary signals The connector is located on the edge of the board making the signals accessible from inside the computer enclosure BNC label1 2 Signal on DVI connector 0 Signa...

Страница 42: ...synchronization signals and transmit receive auxiliary signals Matrox Solios GigE supports acquisition from up to 4 GigE Vision compliant video sources You can connect one GigE Vision compliant video...

Страница 43: ...er it will also function correctly with 100 Mbps Fast Ethernet 100BASE T and 10 Mbps Ethernet 10BASE T networks It is recommended that you use Matrox Solios GigE with Gigabit Ethernet networks to ensu...

Страница 44: ...44 Chapter 2 Hardware installation...

Страница 45: ...Chapter 3 Chapter 3 Using multiple Matrox Solios boards This chapter explains how to use multiple Matrox Solios boards...

Страница 46: ...ce Simultaneous image capture from different boards You can simultaneously capture images from video sources attached to different Matrox Solios boards however the number of video sources from which y...

Страница 47: ...he list of platforms that are known to be compatible with Matrox Solios are available on the Matrox web site under the board s compatibility list To measure the available bandwidth of the PCIe PCI PCI...

Страница 48: ...48 Chapter 3 Using multiple Matrox Solios boards...

Страница 49: ...Chapter 4 Chapter 4 Matrox Solios hardware reference This chapter explains the architecture features and modes of the Matrox Solios eCL XCL Matrox Solios eA XA and Matrox Solios GigE hardware...

Страница 50: ...well as pin assignments for the various connectors can be found in Appendix B Technical information Video to PCI X Bridge Acquisition memory 32 64 128 256 MB PCI X to PCI X XCL XA or PCI X to PCIe eC...

Страница 51: ...ifferent input format or independent path s for simultaneous acquisition MIL Lite uses the concept of a data input channel to identify which input source to use when several of its type are connected...

Страница 52: ...on Matrox Solios eCL XCL dual Base single Medium boards are available in two maximum frequencies standard Camera Link speed and fast Camera Link speed Matrox Solios eCL XCL has one acquisition path ex...

Страница 53: ...pliant sources or up to 64 bits when acquiring from non standard time multiplexed sources Finally a Full type acquisition path supports up to 64 bits of video data when acquiring from Camera Link comp...

Страница 54: ...o not need to be identical when running in dual Base mode Video to PCI X bridge Acquisition section of Matrox Solios XCL B PSG MDR 26 connector ChannelLink Receiver Clock Data 24 Syncs 4 SerTFG SerTC...

Страница 55: ...ctors TTL buffers Aux In 4 Aux Out 4 HSYNC Out 2 VSYNC Out 2 Clock Out 2 Optocoupler Aux I Os 6 ChannelLink Receiver 2 Clock Data 24 Syncs 4 24 LUTs LUTs 32 32 Cam Ctrl 4 Cam Ctrl 4 LVDS drivers LVDS...

Страница 56: ...rs OptoAux 4 DB 44 and DB 9 connectors TTL buffers Aux In 4 Aux Out 2 HSYNC Out 1 VSYNC Out 1 Clock Out 1 Optocoupler Aux I Os 4 ChannelLink Receiver 2 Clock Data 24 Syncs 4 Cam Ctrl 4 LVDS drivers LV...

Страница 57: ...ector ChannelLink Receiver 1 Clock Data 24 Syncs 4 SerTFG SerTC Second MDR 26 connector UART LVDS drivers and receivers OptoAux 4 DB 44 and DB 9 connectors TTL buffers Aux In 4 Aux Out 2 HSYNC Out 1 V...

Страница 58: ...Matrox Solios eCL XCL dual Base single Medium can write to two per acquisition path when in dual Base mode and four when in single Medium mode Matrox Solios eCL XCL F can Video sources supported per...

Страница 59: ...k receivers Matrox Solios eCL XCL B uses one ChannelLink receiver for video input s Matrox Solios eCL XCL dual Base single Medium uses two ChannelLink receivers that can be used synchronously single M...

Страница 60: ...and sends them to the LUTs The demultiplexer can only deserialize video inputs that when combined total a maximum depth of 48 bits per acquisition path Lookup tables Matrox Solios eCL XCL has on board...

Страница 61: ...r or eight 256 entry 8 bit LUTs 4 palettes of one two three or four 1024 entry 8 or 16 bit LUTs 1 palette of one two three or four 4096 entry 8 or 16 bit LUTs Instead of being mapped through a LUT 14...

Страница 62: ...edium mode only one PSG can be used The PSGs are responsible for managing all video timing synchronization triggering exposure and user defined input and output signals Each PSG allows for independent...

Страница 63: ...1 0 Trigger input 3 0 1 2 0 1 0 1 Field polarity input 1 0 0 0 Timer clock input 1 0 Quadrature input4 4 Note that a rotary encoder with quadrature output transmits a two bit code The table entries 0...

Страница 64: ..._IN0 3 P0_OPTO_AUX_IN1 3 OPTO_AUX_IN0 OPTO_AUX_IN1 P0_LVDS_AUX_IN0 3 P0_LVDS_AUX_IN1 LVDS_AUX_IN0 LVDS_AUX_IN1 P0_LVDS_AUX_OUT0 P0_LVDS_AUX_OUT1 P1_LVDS_AUX_OUT0 P1_LVDS_AUX_OUT1 CC1 CC2 CC3 CC4 CC1 C...

Страница 65: ...with data LVDS dedicated signals2 3 CL connect 0 CL connect 1 CL connect 0 CL connect 1 CC1 CC2 CC3 CC4 CC1 CC2 CC3 CC4 Frame valid input 0 1 0 1 1 0 VSYNC output 0 1 0 0 0 0 P0_LVDS_VSYNC_OUT 1 1 0...

Страница 66: ...if replaced with the optional DB 9 connector from the SOLCLBACCxxPAK accessory kit less auxiliary signals are available see the pinout of the auxiliary I O connector in Appendix B Technical informati...

Страница 67: ...that is internally generated Each exposure timer can use its PSG s clock generator which can generate a single clock with a programmable frequency of 0 8 to 100 MHz Timers can only use the clock gener...

Страница 68: ...ou can also program two path independent auxiliary signals as trigger input signals When received in TTL format directly the signal must have a maximum amplitude of 5 V A signal over 2 V is considered...

Страница 69: ...atrox Solios eCL XCL boards1 feature a quadrature decoder that can decode input from a rotary encoder with quadrature output This type of encoder a quadrature encoder is a device that provides informa...

Страница 70: ...eets specifications to an auxiliary input signal or auxiliary I O signals in input mode configured as a user defined signal your application can then interpret this user defined signal as required You...

Страница 71: ...s Grabbed data can be converted into YUV and YCbCr formats in the color space converter of the Video to PCI X bridge Each acquisition path has two selectable inputs A or B and performs AC coupling on...

Страница 72: ...ition path 2 Independent acquisition path 1 DVI connectors 0 and 1 LVDS TTL drivers and receivers Opto couplers Aux In Aux In Aux Out DB 44 and DB 9 connectors 8 8 4 Only acquisition path 0 is availab...

Страница 73: ...65 MHz Bandwidth eA XA Single 130 Mbytes sec eA XA Dual 260 Mbytes sec eA XA Quad 520 Mbytes sec Analog bandwidth 3 db cutoff frequency 100 MHz Configuration Asynchronous video sources supported 1 Acq...

Страница 74: ...csofthe signal whileblocking the static DC characteristics This produces a signal that has an average DC level of 0 Volts regardless of average picture level or DC offset of the incoming signal In eff...

Страница 75: ...t part of the video signal to 1 V which is at the top of the A D conversion range The gain adjustment range is between 0 and 4 in 4096 step increment 12 bit resolution Beforepassing to theDCrestoreand...

Страница 76: ...B cutoff frequency of 33 MHz The second filter has a 3 dB cutoff frequency of 7 5 MHz useful for RS 170 and CCIR video sources All filters provide 80 dB decade or 24 dB octave of attenuation for frequ...

Страница 77: ...on Matrox Solios eA XA can operate in either slave or master mode Slave mode In slave mode the video source provides the synchronization information to Matrox Solios eA XA It can accept any one of the...

Страница 78: ...e line locked mode Since the signal from the video source is used as a reference the PLL can produce a clock signal that is a multiple of it If the video source supplies a clock signal within the inpu...

Страница 79: ...h Max signals 1 TTL aux input2 TTL aux output2 Opto aux input3 TTL LVDS aux input4 TTL LVDS aux output4 P0_TTL_AUX TRIG _IN P1_TTL_AUX TRIG _IN P2_TTL_AUX TRIG _IN P3_TTL_AUX TRIG _IN P0_TTL_AUX EXP _...

Страница 80: ...xiliary I O connector 1 DB 9 4 On external auxiliary I O connector 0 DB 44 Type of signal Path Max signals 1 TTL aux input2 TTL aux output2 Opto aux input3 TTL LVDS aux input4 TTL LVDS aux output4 P0_...

Страница 81: ...in 1 out P0_LVDS_TTL_VSYNC_IO in out 1 1 in 1 out P1_LVDS_TTL_VSYNC_IO in out 2 1 in 1 out P2_LVDS_TTL_VSYNC_IO in out 3 1 in 1 out P3_LVDS_TTL_VSYNC_IO in out CSYNC or HSYNC4 0 1 in 1 out P0_LVDS TTL...

Страница 82: ...ent as a composite synchronization pulse along with the video signal With interlaced video sources you can typicallyestablish which field is being input by noting the phase shift between the horizonta...

Страница 83: ...video source such as a strobe The exposure signals can be output using auxiliary output signals The exposure timers are 24 bit timers allowing each to count up to 16777215 clock ticks before resetting...

Страница 84: ...ent auxiliary signals as trigger input signals these can be received in LVDS TTL or LVTTL When received in TTL format directly the signal must have a maximum amplitude of 5 V when received in LVTTL fo...

Страница 85: ...signal your application can then interpret this user defined signal as required You can specify the on off state of a required output signal and have the PSG generate and route it to an auxiliary out...

Страница 86: ...nding on the input format using the color space converter of the Video to PCI X bridge to Video to PCI X Bridge Image reconstructor GigE Vision filter LVDS receivers TTL buffers Optocoupler Auxiliary...

Страница 87: ...vert incoming images to the following formats Maximum Number of bytes line including sync and blanking 64 K Number of lines frame including sync and blanking 64 K Pixel clock 10 100 1000 Mbps Bandwidt...

Страница 88: ...rly The image reconstructor has four image contexts which in essence provide 4 independent acquisition paths Auxiliary I O controller Auxiliary signals Matrox Solios GigE features an auxiliary I O con...

Страница 89: ...in output mode can be set to exposure output signal 0 Notethatfor Matrox Solios GigE the synchronization timing and control signals are not dependent on an acquisition path and by extension neither ar...

Страница 90: ...ype of signal Signal number In Out OPTO aux in LVDS aux in TTL aux I O TTL aux out AUX TRIG _OPTO_IN0 AUX TRIG _OPTO_IN1 AUX TRIG _OPTO_IN2 AUX TRIG _OPTO_IN3 AUX TRIG _LVDS_IN4 AUX TRIG _LVDS_IN5 AUX...

Страница 91: ...Out x 8 In Out x 9 In Out x 10 Out x 11 Out x 12 Out x 13 Out x 14 Out x 15 Out x 16 Out x 17 Out x Type of signal Signal number In Out OPTO aux in LVDS aux in TTL aux I O TTL aux out AUX TRIG _OPTO_I...

Страница 92: ...through an opto coupler The voltage difference across the positive and negative components of the signal must be between 4 06 V and 9 165 V for logic high and between 5 0 V and 0 8 V for logic low You...

Страница 93: ...sive Therefore when using the slowest internal clock the 16 bit timers can generate an exposure signal with a duration of up to 42 95 secs active time delay A clock from an external source In this cas...

Страница 94: ...To avoid triggering a timer at an inappropriate time for example before the current grab is complete the auxiliary I O controller supports an arm mechanism for each timer When a timer is set to genera...

Страница 95: ...exposure signals This allows you to generate for example multiple pulses or more complex pulses on one signal The two exposure signals must be generated from the same group of exposure timers either e...

Страница 96: ...fy your application s needs for example to perform a Bayer conversion Possible processing operations To use the Processing FPGA you must configure it with an FPGA configuration that defines the approp...

Страница 97: ...a data rate of 462 Mbits sec for a total of 924 Mbytes sec per direction PCI X interface The 64 bit PCI X interface allows the Processing FPGA to communicate with the Host It is 64 bits wide and runs...

Страница 98: ...see the section JTAG connector in Appendix B Technical information Video to PCI X bridge The video to PCI X bridge is capable of high speed transfers to acquisition memory to the optional Processing...

Страница 99: ...e converter can also perform color kill The equations for the conversion are described in the following table Color space conversion Equations RGB to YUV Y 0 299 R 0 587 G 0 114 B U 0 169 R 0 331 G 0...

Страница 100: ...Solios eCL XCL F supports up to 256 Mbytes of 110 MHz SDRAM with a bandwidth of 1 76 Gbytes Optional memory If the optional Processing FPGA is installed on the board Matrox Solios supports up to 256 M...

Страница 101: ...entional PCI bus specification To communicate with the Host Matrox Solios XCL and XA can transfer data using either the Host s PCI or PCI X bus depending on the slot used by the board Matrox Solios eC...

Страница 102: ...a 32 bit PCI slot 266 Mbytes sec for a 66 MHz 32 bit PCI slot and 532 Mbytes sec for a 66 MHz 64 bit PCI slot Using the PCIe PCI PCI X bus Matrox Solios can also access Host physically contiguous non...

Страница 103: ...Appendix A Appendix A Glossary This appendix defines some of the specialized terms used in the Matrox Solios documentation...

Страница 104: ...is known as the horizontal blanking period The portion of a video signal after the end of a frame and before the beginning of a new frame is known as the vertical blanking period Contiguous memory A...

Страница 105: ...e a strobe light Exposure time Refers to the period during which the image sensor of a video source is exposed to light As the length of this period increases so does the image brightness Field One of...

Страница 106: ...al synchronization signal The part of a video signal that indicates the end of a line and the start of a new one See also vertical synchronization signal Interlaced scanning Describes a transfer of da...

Страница 107: ...used for processing QDRII SRAM allows the Processing FPGA to access data faster than with DDR SDRAM Real time processing The processing of an image as quickly as the next image is grabbed Also known...

Страница 108: ...handles asynchronous communication through a serial interface for example RS 232 or LVDS Vertical blanking period The portion of a video signal after the end of a frame and before the beginning of a n...

Страница 109: ...Appendix B Appendix B Technical information This appendix contains information that might be useful when installing your Matrox Solios board...

Страница 110: ...it architecture IA32 or equivalent A relatively up to date PCIe PCI PCI X chipset The list of platforms that are known tobe compatible with MatroxSoliosare available ontheMatroxwebsite under the board...

Страница 111: ...e length of the cable used Supports frame and line scan video sources The min max length for an image and min max width for a line are as follows Captured data can be converted into YUV or YCbCr forma...

Страница 112: ...tes sec of memory bandwidth Separate LVDS pixel clock HSYNC and VSYNC outputs Three TTL auxiliary I O signals trigger field polarity or user defined input or exposure or user defined output See the Ma...

Страница 113: ...ink boards support a maximum frequency of 85 MHz In dual Base mode the programmable LUTs can be operated in the following configurations per acquisition path1 8 palettes of one two three or four 256 e...

Страница 114: ...gle Medium mode and Matrox Solios eCL XCL F Matrox Solios eCL XCL dual Base in single Medium mode supports a single video source in the Camera Link Medium configuration while Matrox Solios eCL F suppo...

Страница 115: ...ndwidth Six TTL auxiliary I O signals trigger field polarity or user defined input or exposure or user defined output See the Matrox Solios hardware reference chapter for supported configurations Four...

Страница 116: ...quire from one dual tap monochrome video source With Matrox Solios eA XA Quad acquisition paths can be combined to acquire from Component RGB video source Two dual tap monochrome video sources Capture...

Страница 117: ...reference chapter for supported configurations RS 232 serial port Bi color status LED One two or four 1024 entry 8 or 16 bit programmable LUTs depending on the board 64 128 256 Mbytes of 83 MHz DDR S...

Страница 118: ...r user defined input or exposure or user defined output See the Matrox Solios hardware reference chapter for supported configurations Two LVDS auxiliary input signals timer trigger timer clock or user...

Страница 119: ...ion Output current loaded 100 Ohm 20 mA typ Output voltage loaded 100 Ohm differential 250 mV min to 450 mV max common mode 1 125 V min to 1 375 V max low 1 02 V typ 0 9 V min high 1 33 V typ 1 6 V ma...

Страница 120: ...ltage loaded 100 Ohm differential 250 mV min to 450 mV max common mode 1 125 V min to 1 375 V max low 1 02 V typ 0 9 V min high 1 33 V typ 1 6 V max Input signals in TTL format No termination Pulled u...

Страница 121: ...ed 100 Ohm 20 mA typ Output voltage loaded 100 Ohm differential 250 mV min to 450 mV max common mode 1 125 V min to 1 375 V max low 1 02 V typ 0 9 V min high 1 33 V typ 1 6 V max Input signals in TTL...

Страница 122: ...ce current 0 5 A Amplitude 0 25 V min to 1 2 V max terminated if using a maximum gain factor of 4 0 5 V min to 2 4 V max terminated if using a maximum gain factor of 2 I O Specifications Input signals...

Страница 123: ...n the analog video input DVI connectors for all TTL output signals except for TTL auxiliary signals that can be configured for exposure output 33 Ohm series impedance High level output current 24 mA m...

Страница 124: ...itor to ground Input current 1 A min to 1 A max Input voltage threshold low of 0 8 V max high of 2 0 V min High level output current 32 mA max Low level output current 64 mA max Output voltage low of...

Страница 125: ...inger to top edge of board XCL B 16 76 L x 6 44 H x 0 16 W cm 6 6 x 2 536 x 0 062 from bottom edge of goldfinger to top edge of board eCL XCL dual Base single Medium and eCL XCL F 19 05 L x 10 67 H x...

Страница 126: ...ernal auxiliary I O connector The following illustrates Matrox Solios eCL XCL B Note that the Matrox Solios eCL XCL B signal names have a ranking that reflects the number of signals of that type forma...

Страница 127: ...xposure output 0 or 1 user defined output 0 or 1 4 CC2 Camera control output 2 negative Specific to the acq path exposure output 0 or 1 user defined output 0 or 1 17 CC2 Camera control output 2 positi...

Страница 128: ...damage both the VGA device and the Matrox Solios board The pinout for the auxiliary I O connector is as follows 1 If you purchase the SOLCLBACCxxPAK accessory kit you can replace the DB 15 auxiliary I...

Страница 129: ..._AUX_IN0 Opto isolated auxiliary input 0 negative See pin 15 for more information 10 GND Ground 11 5 P0_OPTO_AUX_IN1 Opto isolated auxiliary input 1 negative See pin 12 for more information 12 4 P0_OP...

Страница 130: ...are two external auxiliary I O connectors HD 44 and DB 9 these allow you to access the signalsof the internal auxiliary I O connector from outside the computer enclosure The following illustrates Matr...

Страница 131: ...e output 0 or 1 user defined output 0 or 1 15 CC4 Camera control output 4 positive Specific to the acq path exposure output 0 or 1 user defined output 0 or 1 3 CC3 Camera control output 3 positive Spe...

Страница 132: ...X1 Video input data X1 negative 12 X0 Video input data X0 positive 25 X0 Video input data X0 negative 13 Inner shield Ground 26 Inner shield Ground Pin Signal Description Pin Signal Description Pin S...

Страница 133: ...can be routed onto it 1 16 31 15 30 44 Pin Signal Description 1 P1_TTL_AUX_IO_1 TTL auxiliary input output 1 for acq path 1 Supported signals exposure output 0 exposure output 3 trigger input 1 user d...

Страница 134: ...auxiliary output 1 for acq path 1 negative See pin 2 for more information 18 P1_LVDS_AUX_OUT0 LVDS auxiliary output 0 for acq path 1 negative See pin 33 for more information 19 P0_LVDS_AUX_OUT1 LVDS...

Страница 135: ..._OUT0 LVDS auxiliary output 0 for acq path 1 positive Supported signals exposure output 0 user defined output 5 34 GND Ground 35 P1_TTL_AUX_IO_0 TTL auxiliary input output 0 for acq path 1 Supported s...

Страница 136: ...O signals accessible outside the computer enclosure The pinout for this connector is as follows The description of each positive auxiliary signal states whether the signal is specific to an independen...

Страница 137: ...S_AUX_IN0 LVDS auxiliary input 0 for acq path 0 negative See pin 8 for more information 4 P0_OPTO_AUX_IN1 Opto isolated auxiliary input 1 for acq path 0 positive Supported signals trigger input 1 user...

Страница 138: ...HSYNC output for acq path 0 negative A2 GND Ground B2 P1_LVDS_HSYNC_OUT HSYNC output for acq path 1 negative A3 P1_LVDS_HSYNC_OUT HSYNC output for acq path 1 positive B3 GND Ground A4 P0_LVDS_VSYNC_O...

Страница 139: ...for acq path 1 positive B17 P1_LVDS_AUX_OUT1 LVDS auxiliary output 1 for acq path 1 negative A18 TTL_AUX_IO_1 TTL auxiliary input output 1 for an unspecified acq path B18 GND Ground A19 P0_LVDS_CLK_O...

Страница 140: ...egin debugging you must first enable the connector by installing a jumper on the adjacent 2 pin connector J2 For further information on debugging with the JTAG connector refer to the Quartus II docume...

Страница 141: ...these allow you to access the signalsof the internal auxiliary I O connector from outside the computer enclosure The following illustrates Matrox Solios XA and an adapter board Note that the Matrox S...

Страница 142: ...utes the synchronization signals to the appropriate pins Note that synchronization and clock signals can be either LVDS or TTL when TTL they are expected on the pin denoted as positive The pinout for...

Страница 143: ...TTL_CHSYNC_IO CSYNC input or HSYNC input output for acq path 1 positive C2 P1_VID_IN_A Video input A for acq path 1 AC DC 11 GND Ground C3 P2_VID_IN_A Video input A for acq path 2 AC DC 12 P0_LVDS TT...

Страница 144: ..._IN TTL auxiliary input for acq path 3 Supported signals trigger input 0 main purpose field input or user defined input 0 7 P3_RS232_RxD RS 232 serial input to acq path 3 of frame grabber UART 23 P2_...

Страница 145: ...his connector the board can both transmit and receive synchronization signals at the same time In addition all the signals can be either LVDS or TTL when TTL they are expected on the pin denoted as po...

Страница 146: ...3 GND Ground 4 P2_LVDS TTL_AUX_OUT1 Auxiliary output 1 for acq path 2 negative See pin 20 for more information 5 LVDS TTL_AUX_IN5 Auxiliary input 5 for an unspecified acq path negative See pin 6 for m...

Страница 147: ...trigger input 3 13 GND Ground 14 GND Ground 15 P0_LVDS TTL_AUX_OUT0 Auxiliary output 0 for acq path 0 positive Supported signals user defined output 0 exposure output 0 or HSYNC output 16 LVDS TTL_AU...

Страница 148: ...pported signals user defined output 0 exposure output 0 or HSYNC output 34 LVDS TTL_AUX_IN0 Auxiliary input 0 for an unspecified acq path negative See pin 35 for more information 35 LVDS TTL_AUX_IN0 A...

Страница 149: ...or HSYNC output 44 P0_LVDS TTL_AUX_OUT1 Auxiliary output 1 for acq path 0 positive Supported signals user defined output 1 exposure output 1 or VSYNC output 1 Note that only signals defined for acqui...

Страница 150: ...of signals that can be routed onto it 9 6 1 5 Pin Signal1 Description 1 P2_OPTO_AUX TRIG _IN Opto isolated auxiliary input for acq path 2 positive Supported signals trigger input 1 or user defined in...

Страница 151: ...essible so that an easily sourced connector of a reasonable size can be used Note that the clock signals are not accessible from the adapter board The pins for auxiliary signals carry unidirectional s...

Страница 152: ...0 A4 GND Ground B4 P1_LVTTL_CLK_OUT Clock output for acq path 1 A5 GND Ground B5 P1_LVTTL_CLK_IN Clock input for acq path 1 A6 GND Ground B6 P2_LVTTL_CLK_OUT Clock output for acq path 2 A7 GND Ground...

Страница 153: ...q path B21 LVTTL_AUX_IN3 Auxiliary input 3 for an unspecified acq path A22 LVTTL_AUX_IN4 Auxiliary input 4 for an unspecified acq path B22 LVTTL_AUX_IN5 Auxiliary input 5 for an unspecified acq path A...

Страница 154: ...st enable the connector by installing a jumper on the adjacent 2 pin connector J4 for Matrox Solios eA J5 for Matrox Solios XA For further information on debugging with the JTAG connector refer to the...

Страница 155: ...vice to the board through the external auxiliary I O connector The following illustrates Matrox Solios GigE and the bracket with the auxiliary I O connector Note that the Matrox Solios GigE signal nam...

Страница 156: ...pin internal auxiliary I O connector on the board making the I O signals accessible outside the computer enclosure The pinout for this connector is as follows The description of each positive auxilia...

Страница 157: ...re information 14 AUX TRIG _LVDS_IN5 LVDS auxiliary 5 input for an unspecified acq path negative See pin 12 for more information 15 NC Not connected 16 AUX TRIG _OPTO_IN0 Opto isolated auxiliary 0 inp...

Страница 158: ...liary 10 output for an unspecified acq path Supported signals exposure output 0 7 user defined 10 output 36 AUX EXP _TTL_OUT15 TTL auxiliary 15 output for an unspecified acq path Supported signals exp...

Страница 159: ...ecified acq path positive 8 AUX TRIG _OPTO_IN3 Opto isolated auxiliary 3 input for an unspecified acq path negative 9 GND Ground 10 GND Ground 11 AUX TRIG _TTL_IO_6 TTL auxiliary 6 input output for an...

Страница 160: ...0 pin male JTAG connector for debugging and probing internal signals of the FPGA The pin assignment as used in JTAG mode is as follows Manufacturer NorComp Inc Connector 172 E09 102 031 Backshell 970...

Страница 161: ...a Corporation To begin debugging you must first enable the connector by installing a jumper on the adjacent 2 pin connector J2 For further information on debugging with the JTAG connector refer to the...

Страница 162: ...162 Appendix B Technical information...

Страница 163: ...Appendix C Appendix C Major revisions of Matrox Solios boards This appendix lists the major revisions of the Matrox Solios boards that are RoHS compliant...

Страница 164: ...A D This was done to ensure availability 003 Improved product packaging 004 Replaced a pull up resistor so that stronger PCIe interrupt signals could be transmitted This was a preventive action 005 C...

Страница 165: ...ion 201 Added termination resistors to the interface of the Processing FPGA This was a corrective action 202 Moved to secondary source for A D This was done to ensure availability 203 Improved product...

Страница 166: ...r more information refer to product bulletin MIPB 77 105 Changed product packaging 106 Added pull up resistors to the interface of the CPLD This was a corrective action For more information refer to p...

Страница 167: ...101 Added termination resistors to the interface of the Processing FPGA This was a corrective action 102 Added a JTAG connector that can be used to validate an FPGA configuration loaded in the Process...

Страница 168: ...ndix C Major revisions of Matrox Solios boards RoHS compliant versions of Matrox Solios GigE Part number Version Description SOL6M4GE 112 First active product version SOL1M4GE 105 First active product...

Страница 169: ...Appendix D Appendix D Acknowledgments This appendix lists the copyright information regarding third party material used to implement components on the Matrox Solios board...

Страница 170: ...ther the name of the author nor the names of other contributors may be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDE...

Страница 171: ...Link video input connectors 127 131 Camera Link supported configurations 12 52 channel switching Matrox Solios eA XA 74 ChannelLink receivers 59 color space conversion 99 COM port 19 77 composite syn...

Страница 172: ...Inspector 22 Matrox Intellicam 23 51 Matrox Solios eA XA 15 19 39 72 116 122 141 A D converters 76 acquisition features 15 71 acquisition paths 73 acquisition rate 73 attenuator 75 auxiliary signals 8...

Страница 173: ...8 73 86 multiple boards 46 O offset controller Matrox Solios eA XA 75 optional features 118 P PCI slot 23 30 PCIe slot 23 30 PCI X slot 23 30 pixel clock Matrox Solios eA XA 78 83 Matrox Solios eCL XC...

Страница 174: ...ta 21 101 triggers Matrox Solios eA XA 84 Matrox Solios eCL XCL 68 U UART 19 62 77 defined 108 V vertical blanking period 108 vertical synchronization defined 108 vertical synchronization signals 77 v...

Страница 175: ...in accordance with the instruction manual may cause harmful interference to radio communications Operation of these devices in a residential area is likely to cause harmful interference in which case...

Страница 176: ...lectrical and Electronic Equipment WEEE Europe English European user s information Directive on Waste Electrical and Electronic Equipment WEEE Please refer to the Matrox Web site www matrox com enviro...

Страница 177: ...BE Pb Hg Cd Cr VI PBB PBDE YPDSB009FS0S2 D SUB X O O O O O YSF0440X18750 X O O O O O YIF00030C08B0 X O O O O O YDK0340M0 X O O O O O YDK140M0 X O O O O O YIC11486XXXM0 X O O O O O YIL01085CXXM1 X O O...

Страница 178: ...YPDSB009FS0S2 D SUB X O O O O O YSF0440X18750 X O O O O O YIF00030C08B0 X O O O O O YCCT10WMM0 X O O O O O YDR0001M0 X O O O O O YIC11486XXXM0 X O O O O O YIL01117CXXM4 X O O O O O YIL01580CXXM1 X O O...

Страница 179: ...Material disclosure table for SOL6M4GE Pb Hg Cd Cr VI PBB PBDE YIF00040C07B0 X O O O O O YDK140M0 X O O O O O YQMN4884M0 1 026 7 X O O O O O YRSR000A00M0 X O O O O O YPRJ45010FS0S0 RJ 45 X O O O O O...

Страница 180: ...sure table for SOL6M4GE30546 Pb Hg Cd Cr VI PBB PBDE YIF00040C07B0 X O O O O O YDK140M0 X O O O O O YQMN4884M0 1 026 7 X O O O O O YRSR000A00M0 X O O O O O YIF00030C05B1 X O O O O O YPRJ45010FS0S0 RJ...

Страница 181: ...XXM0 X O O O O O YIL01085CXXM1 X O O O O O YLCU820M1 X O O O O O YQMN4884M0 1 026 7 X O O O O O YRLR075C01M0 X O O O O O YRSR000A00M0 X O O O O O YLCU470M0 X O O O O O YLCU680M2 X O O O O O YLC4U70M1...

Страница 182: ...X O O O O O YLC6U80M2 X O O O O O YSF0440X18750 X O O O O O YIF00030C08B0 X O O O O O YDK140M0 X O O O O O YDR0001M0 X O O O O O YIL01117CXXM4 X O O O O O YIL01580CXXM1 X O O O O O YLCU820M1 X O O O...

Страница 183: ...M1 X O O O O O YLC6U80M2 X O O O O O YSF0440X18750 X O O O O O YIF00030C07B0 X O O O O O YDK140M0 X O O O O O YDR0001M0 X O O O O O YIL01117CXXM4 X O O O O O YIL01580CXXM1 X O O O O O YLCU820M1 X O O...

Страница 184: ...XXM0 X O O O O O YIL01085CXXM1 X O O O O O YLCU820M1 X O O O O O YQMN4884M0 1 026 7 X O O O O O YRLR075C01M0 X O O O O O YRSR000A00M0 X O O O O O YLCU470M0 X O O O O O YLCU680M2 X O O O O O YLC4U70M1...

Страница 185: ...X O O O O O YLC6U80M2 X O O O O O YSF0440X18750 X O O O O O YIF00030C08B0 X O O O O O YDK140M0 X O O O O O YDR0001M0 X O O O O O YIL01117CXXM4 X O O O O O YIL01580CXXM1 X O O O O O YLCU820M1 X O O O...

Страница 186: ...XXM0 X O O O O O YIL01085CXXM1 X O O O O O YLCU820M1 X O O O O O YQMN4884M0 1 026 7 X O O O O O YRLR075C01M0 X O O O O O YRSR000A00M0 X O O O O O YLCU470M0 X O O O O O YLCU680M2 X O O O O O YLC4U70M1...

Страница 187: ...X O O O O O YLC6U80M2 X O O O O O YSF0440X18750 X O O O O O YIF00030C08B0 X O O O O O YDK140M0 X O O O O O YDR0001M0 X O O O O O YIL01117CXXM4 X O O O O O YIL01580CXXM1 X O O O O O YLCU820M1 X O O O...

Страница 188: ...E YPDSB009FS0S2 D SUB X O O O O O YSF0440X18750 X O O O O O YDK0340M0 X O O O O O YDK140M0 X O O O O O YIC11486XXXM0 X O O O O O YIL01085CXXM1 X O O O O O YQMN4884M0 1 026 7 X O O O O O YRLR075C01M0 X...

Страница 189: ...YPDSB009FS0S2 D SUB X O O O O O YSF0440X18750 X O O O O O YCCT10WMM0 X O O O O O YDR0001M0 X O O O O O YIC11486XXXM0 X O O O O O YIL01117CXXM4 X O O O O O YIL01580CXXM1 X O O O O O YQMN9926M2 1 026 7...

Страница 190: ...E YPDSB009FS0S2 D SUB X O O O O O YSF0440X18750 X O O O O O YIF00030C07B0 X O O O O O YDK0340M0 X O O O O O YDK140M0 X O O O O O YIC11486XXXM0 X O O O O O YIL01085CXXM1 X O O O O O YQMN4884M0 1 026 7...

Страница 191: ...YPDSB009FS0S2 D SUB X O O O O O YSF0440X18750 X O O O O O YIF00030C07B0 X O O O O O YCCT10WMM0 X O O O O O YDR0001M0 X O O O O O YIC11486XXXM0 X O O O O O YIL01117CXXM4 X O O O O O YIL01580CXXM1 X O O...

Страница 192: ...E YPDSB009FS0S2 D SUB X O O O O O YSF0440X18750 X O O O O O YIF00030C08B0 X O O O O O YDK0340M0 X O O O O O YDK140M0 X O O O O O YIC11486XXXM0 X O O O O O YIL01085CXXM1 X O O O O O YQMN4884M0 1 026 7...

Страница 193: ...on Matrox hardware products or any software including without limitation the Software Package even if packaged is sold with Matrox Hardware The Software Package provided by Matrox is not covered under...

Страница 194: ...NEITHER MATROX NOR ANY OF ITS THIRD PARTY SUPPLIERS MAKES ANY OTHER WARRANTY OF ANY KIND WHETHER EXPRESSED OR IMPLIED WITH RESPECT TO MATROX HARDWARE MATROX SPECIFICALLY DISCLAIMS AND THE PURCHASER B...

Страница 195: ...the warranty period Matrox does not offer any other warranty 1 12 The Licensee shall be responsible for all applicable taxes duties and customs fees on any replacement unit as well as all transport i...

Страница 196: ......

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