LSI L64777, Техническое руководство

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2-20 Modulator Architecture
SSTARTIN input signal can preset the phase of the inverted
SYNC_BYTE and the whole scrambler sequence.
The microprocessor can switch off the scrambler module through
Register 3 (see Section 4.1.4, “Register 3,” page 4-5). The selected
microprocessor control applies the sequence of Start, Run, and Disable
modes, depending on the programmed sync block length values in
Register 4 (see page 4-6).
2.7 Reed-Solomon Encoder
Reed-Solomon (RS) error correction codes are systematic and operate
on bytes rather than single-bit data streams. The codes are expressed
by convention as two numbers, the first indicating the total code word
length (N), and the second indicating the number of message bytes (K).
The difference between these two numbers (N
−
K) is the number of
check bytes.
DVB uses this generator polynomial for RS codes:
where R = 16 (checkbytes), and
α
is a root of the binary primitive
polynomial:
A data byte (d
7
, d
6
,...d
1
, d
0
) is identified with the element
d
7
α
7
+ d
6
α
6
+...+ d
1
α
+ d
0
in GF (256), the finite field with 256 elements.
The error-correcting power of an RS code is related to the number of
redundant check symbols in its code words. In general, an RS code with
2t check symbols per code word can correct up to “t” byte errors per
code word. Higher redundancy allows more errors to be corrected.
ECC devices have a specific lexicon associated with their ability to
correct transmission messages; the terms used for variables in the
Reed-Solomon Core are as follows:
x
α
i
+
( )
i 0 =
R 1
–
∏
x
8
x
4
x
3
x
2
1
+ + + +