LSI Logic Confidential
Master DMA Registers
8-25
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
8.7.4
Host DMA BaseAddress and LimitAddress Registers (CBus
Address: 0x6006C and 0x60070)
The host DMA base address register at control bus address 0x6006C
specifies the SDRAM address for the beginning of the host DMA circular
SDRAM buffer. The host DMA limit address register at control bus
address 0x60070 specifies the SDRAM address for the first byte after the
host DMA buffer. When the host DMA next address reaches the value in
the host DMA limit address register, it is reloaded with the host DMA
Base Address register value before transferring additional data. The two
least significant and the upper four bits of these registers must be zero.
8.8
Master DMA Registers
All master DMA registers are 32-bit CBus registers which are accessible
to the SPARC core or Host Interface using 32-bit loads or stores.
8.8.1
Master DMA Configuration Register (Cbus Addr: 0x6F000)
This register at control bus address 0x6F000 specifies master DMA
configuration information.
Master DMA Configuration Register
Memory Space Address: 0x6F000
LE
5
If LE is set, master DMA transfers between SDRAM and
the async master bus are byte swapped; otherwise, they
are not swapped. Bits [15:8] of MData are swapped with
[7:0].
1 = Transfers byte swapped
0 = Transfer not byte swapped
31
16
Reserved
15
5
4
3
2
1
0
Reserved
LE
IE
GO
Ainc
BSRD
WRData
Содержание DMN-8600
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