DMN-8600 DVD Recorder System Processor
17-1
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
LSI Logic Confidential
Chapter 17
JTAG Boundary Scan
this chapter describes the JTAG boundary scan and contains the
following sections:
•
Section 17.1, “JTAG Instruction Set”
•
Section 17.2, “Boundary Scan Chain Cells”
The DMN-8600 processor implements a JTAG boundary scan interface
in accordance with IEEE 1149.1. The optional TRST pin is provided to
simplify resetting the tap controller in systems that do not use the JTAG
port. The tap controller must be reset after power-up to enable normal
processor operation.
Note:
The Tap Controller is not reset by RST.
DMN-8600 boundary scan supports only board-level testing (for example,
SAMPLE/PRELOAD and EXTEST instructions); component testing (for
example, the INTEST instruction) is not supported.
Содержание DMN-8600
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