7.2.5 Implemented Measures against Systematic Errors
For the safety compliant system, for development and design, the following measures have been taken to prevent from
systematic errors:
implementation of tables under EN 61508-2 Appendix B
implementation of tables under EN 61508-3 Appendix A
7.2.6 Used Technologies and architecture
For the implementation of the safety related functions the following technologies are used.
HW design is based on C1250, which is proven in use
two channel architecture for safety related functions
cross monitoring of the two channels, realized in HW and SW
fault exclusion for single channel parts
The safety related block diagram of the implementation is:
Figure 6: Safety related block diagram
Where a dual channel architecture is implemented the hardware fault tolerance (HFT) is 1:
Brake Control
STO Switch off
Safe Dig In
MCU (incl. Power Supply and FW)
STO Switch off
Safe Dig Out
Where a single channel architecture is implemented the HFT is 0.
General Infrastructure (PCB, Connectors ...)
Memory
Supply
Safe Address
2S Drive Systems / 0185-1174_E_1V1_SM_C1251-2S / NTI AG
0185-1174_E_1V1_SM_C1251-2S / 2021-11-26 16:43 (Rev. 12500)
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