1
dc1257bf
DEMO MANUAL DC1257B
DESCRIPTION
LTC6416
2 GHz Low Noise Differential
16-Bit ADC Buffer
Demonstration circuit 1257B features the LTC
®
6416, a
2GHz low noise differential 16-Bit ADC buffer driving the
LTC2208, a 16-bit 130Msps ADC. The DC1257B is sup-
plied with a bandpass filter centered at 140MHz between
the buffer and the ADC. The filter center frequency can be
changed to optimize performance at different analog input
frequencies. Both single-ended and differential configura-
tions are supported at the inputs. The DC1257B has been
Demonstration circuit 1257B is easy to set up. Refer to
Figure 1 for proper measurement equipment setup. Table 1
The DC1257B requires DC890 FastDAACs data acquisition
board with PScope System Software. The PScope System
Software is available from the Linear Technology website
at http://www.linear.com/software/.
Apply power to the DC1257B Demonstration Circuit.
Apply
+3.6V across the pins marked OPT and GND, VS and GND.
The DC1257B demonstration circuit requires up to 100mA
from the OPT pin, and up to 700 mA from the VS pin.
L
, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation and PScope is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
developed from the DC996B-B, used to characterize the
LTC2208 family of ADCs.
Use the DC1257B with a DC890 FastDAACS and PScope™
software to collect time and frequency data.
Design files for this circuit board are available at
http://www.linear.com/demo
QUICK START PROCEDURE
HARDWARE SETUP
Table 1: DC1257B SMA Connector and Jumper Descriptions
J2 (A
IN
+
)
Single-Ended/Differential Input.
By default, this is configured as a single-ended input
. Use this connector to supply an input to
the DC1257B. When driven from a 50Ω signal source, no external termination necessary.
J3 (A
IN
–
)
Differential Input.
Not connected by default.
Capacitor C23 can be installed and C25 removed to drive the DC1257B differentially.
J4 (CLK)
Single-Ended Input. This input is designed to be driven by an extremely low jitter 50Ω source. A sinusoidal input of up to 13dBm
is recommended.
JP1 (PGA)
Programmable gain amplifier.
Default to LOW Gain Mode.
This sets the gain of the ADC amplifier to 1.0.
JP2 (RAND)
ADC Digital Output Randomization.
Default to OFF.
This disables randomization.
JP3 (SHDN ADC)
ADC Power Shutdown ADC.
Default to EN.
This results in normal operation.
JP4 (DITH)
ADC Internal Dither Enable.
Default to OFF.
This disables internal dither.
describes the function of each SMA connector and default
settings for the jumpers on the board.
Supply power to the DC890B FastDAACS Board with an
external 6V ±0.5V 1A supply on turrets on G7(+) and G1(–)
or the adjacent 2.1mm power jack. Unless the DC890B
detects external power it will not activate the LVDS mode of
the Xilinx Spartan-III FPGA. The FPGA actively terminates
the LVDS repeaters at the outputs of the LTC2208.
