LT8708
37
Rev 0
Gate Resistors: In some cases it can be beneficial to add
1Ω to 10Ω of resistance between some of the NMOS gate
pins and their respective gate driver pins on the LT8708
(i.e., TG1, BG1, TG2, BG2). Due to parasitic inductance
and capacitance, ringing can occur on SW1 or SW2 when
low capacitance MOSFETs are turned on/off too quickly.
The ringing can be of greatest concern when operating
the MOSFETs or the LT8708 near the rated voltage limits.
Additional gate resistance slows the switching speed,
minimizing the ringing.
Excessive gate resistance can have two negative side ef-
fects on performance:
1. Slowing the switch transition times can also increase
power dissipation in the switch. This is described
above.
2. Capacitive coupling from the SW1 or SW2 pin to the
switch gate node can turn it on when it’s supposed
to be off, thus increasing power dissipation. With
too much gate resistance, this would happen to the
M2 switch when SW1 is rising with positive inductor
current and to the M3 switch when SW2 is rising with
negative inductor current.
Careful board evaluation should be performed when opti-
mizing the gate resistance values. SW1 and SW2 pin ringing
can be affected by the inductor current levels, therefore
board evaluation should include measurements at a wide
range of load currents, V
IN
and V
OUT
. When performing
PCB measurements of the SW1 and SW2 pins, be sure
to use a very short ground post from the PCB ground to
the scope probe ground sleeve in order to minimize false
inductive voltage readings.
C
IN
AND C
OUT
SELECTION
V
IN
and V
OUT
capacitance is necessary to suppress volt-
age ripple caused by discontinuous current moving in and
out of the regulator. A parallel combination of capacitors
is typically used to achieve high capacitance and low
ESR (equivalent series resistance). Dry tantalum, special
polymer, aluminum electrolytic and ceramic capacitors are
all available in surface mount packages. Capacitors with
low ESR and high ripple current ratings, such as OS-CON
and POSCAP are also available.
Ceramic capacitors should be placed near the regulator
input and output to suppress high frequency switching
spikes. A ceramic capacitor, of at least 1μF at the maximum
V
INCHIP
operating voltage, should also be placed from
V
INCHIP
to GND as close to the LT8708 pins as possible.
Due to their excellent low ESR characteristics ceramic
capacitors can significantly reduce input ripple voltage and
help reduce power loss in the higher ESR bulk capacitors.
X5R or X7R dielectrics are preferred, as these materials
retain their capacitance over wide voltage and temperature
ranges. Many ceramic capacitors, particularly 0805 or
0603 case sizes, have greatly reduced capacitance at the
desired operating voltage.
V
IN
Capacitance: Discontinuous V
IN
current is highest in
the buck region due to the M1 switch toggling on and off.
Make sure that the C
IN
capacitor network has low enough
ESR and is sized to handle the maximum RMS current. For
buck operation, the V
IN
RMS current is given by:
I
(IN,RMS)
≅
I
OUT
•
V
OUT
V
IN
•
V
IN
V
OUT
– 1
A
This formula has a maximum at V
IN
= 2•V
OUT
, where
I
(IN,RMS)
= I
OUT
/2. This simple worst-case condition is
commonly used for design because even significant devia-
tions do not offer much relief.
C
IN
is necessary to reduce the V
IN
voltage ripple caused
by discontinuities and ripple of I
IN
. The effects of ESR and
the bulk capacitance must be considered when choosing
the correct capacitor for a given V
IN
ripple.
The V
IN
ripple due to the voltage drop across the bulk
cap ESR
BULK
, without having any ceramic capacitance in
parallel, is approximately:
∆V
(IN,BUCK,BULK)
≅
I
OUT
•ESR
BULK
V
APPLICATIONS INFORMATION
