1
Rev. 0
DESCRIPTION
LT8698S/LT8698S-1
5V 3A, 42V Input USB Charger with Cable Drop
Compensation and Data Line Protection
Demonstration circuit 2688A is a USB charger designed
to power the 5V USB V
BUS
rail with up to 3A from an
input voltage as high as 42V. The DC2688A circuit fea-
tures the
, which is a compact, high
efficiency, high speed synchronous monolithic step-down
switching regulator which features the second-genera-
tion Silent Switcher
®
technology that minimizes EMI and
reduces PCB layout sensitivity. The LT8698S/LT8698S-1
supports a wide variety of portable device charger pro-
files including USB BC 1.2 CDP, DCP, and SDP as well as
common proprietary charger profiles, all of which can
be easily evaluated using the DC2688A demo board. The
LT8698S/LT8698S-1 also features high speed USB 2.0
compliant data line switches, robust data line protection,
and programmable cable drop compensation which main-
tains accurate 5V V
BUS
regulation even when USB sockets
are separated from the LT8698S/LT8698S-1 by a long
cable. These features make the LT8698S/LT8698S-1 well
suited for automotive USB host applications.
There are two assembly versions. The DC2688A-A fea-
tures the LT8698S, while the DC2688A-B features the
LT8698S-1. The difference is that the LT8698S includes
V
IN
hot loop capacitors inside the IC package for improved
EMI/EMC performance, while the LT8698S-1 does not
include these capacitors.
DEMO BOARD INFORMATION
The main power stage of the DC2688A demo board oper-
ates at 2MHz switching frequency by default to minimize
solution size. The jumper JP5 on the demo board deter-
mines the configuration of the SYNC pin of the LT8698S/
LT8698S-1. Setting the jumper JP5 to “FCM W/SSM”
location ties SYNC pin to INTV
CC
which enables forced
continuous mode with spread-spectrum modulation for
improved EMI performance. Moving JP5 to “PSK” loca-
tion enables the pulse-skipping mode which improves
light load efficiency by reducing the switching frequency
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at light load and reducing V
IN
quiescent current between
pulses. To synchronize to an external clock, move JP5
to “FCM W/O SSM or SYNC” location and apply external
clock on the EXT_SYNC turret.
Figure 1 shows a functional Block Diagram of the DC2688A
demo board.
The DC2688A demo board includes a re-timer IC USB2422
whose purpose is to ensure that USB high speed signaling
eye pattern can be measured at test plane 2 as defined by
USB 2.0 specifications, and that such signaling through
the LT8698S/LT8698S-1’s USB data line switches con-
forms to template 1 eye pattern requirements. Please note
that a re-timer IC is not necessary in actual applications
as the USB host controller will reside on the same PCB
board as the LT8698S/LT8698S-1.
The DC2688A demo board includes three headers JP2,
JP3, and JP4, which are used for manual control of the
LT8698S/LT8698S-1’s tristate input pins SEL1, SEL2, and
SEL3. Although these select pins are intended to interface
with a USB host microcontroller, majority of the functions
of the LT8698S/LT8698S-1 may be evaluated by simply
using the manual selection of the SEL1, SEL2, and SEL3
headers on the DC2688A board.
The DC2688A demo board is 3.5-inch × 3.5-inch in size
and has four copper layers with 2oz copper on the outer
layers and 1oz copper on the inner layers. The DC2688A
has controlled impedance transmission lines placed for
high speed differential USB data signaling, in between the
USB-B receptacle, the USB2422 re-timer IC, the LT8698S/
LT8698S-1 data line switches, and the USB-A receptacle,
with a differential characteristic impedance of 90Ω.
The default rated maximum load current of the DC2688A
is 2.4A, with a default R
SENSE
resistor value of 10mΩ.
However, the DC2688A circuit can supply 3A load current
with a R
SENSE
resistor value of 8mΩ.
