- 2-18 -
3) PORT DESCRIPTION
Pin No.
Symbol
I/O
Function
1
D11
I/O
DRAM data signal I/O 11
2
D10
I/O
DRAM data signal I/O 10
3
D9
I/O
DRAM data signal I/O 9
4
D8
I/O
DRAM data signal I/O 8
5
UDQM
O
SDRAM upper byte data mask signal output
6
SDRCK
O
SDRAM clock signal output
7
A11
O
DRAM address signal output 11
8
A9
O
DRAM address signal output 9
9
A8
O
DRAM address signal output 8
10
A7
O
DRAM address signal output 7
11
A6
O
DRAM address signal output 6
12
A5
O
DRAM address signal output 5
13
A4
O
DRAM address signal output 4
14
LDQM
O
SDRAM lower byte data mask signal output
15
NWE
O
DRAM write enable signal output
16
NCAS
O
DRAM CAS control signal output
17
NRAS
O
DRAM RAS control signal output
18
NCS
O
SDRAM chip select signal output
19
A3
O
DRAM address signal output 3
20
A2
O
DRAM address signal output 2
21
A1
O
DRAM address signal output 1
22
A0
O
DRAM address signal output 0
23
DRVDD1
I
Power supply 1 for DRAM interface I/O
24
DVSS1
I
Ground 1 for digital circuits
25
A10
O
DRAM address signal output 10
26
*BA1
O
SDRAM bank selection signal output 1
27
*BA0
O
SDRAM bank selection signal output 0
28
DVDD1
I
Power supply 1 for internal digital circuits
29
SPOUT
O
Spindle drive signal output (absolute value)
30
*SPPOL
O
Spindle drive signal output (polarity)
31
TRVP
O
Traverse drive signal output (positive polarity)
32
*TRVM
O
Traverse drive signal output (negative polarity)
33
*TRVP2
O
Traverse drive signal output 2 (positive polarity)
34
*TRVM2
O
Traverse drive signal output 2 (negative polarity)
35
TRP
O
Tracking drive signal output (positive polarity)
36
*TRM
O
Tracking drive signal output (negative polarity)
37
FOP
O
Focus drive signal output (positive polarity)
38
*FOM
O
Focus drive signal output (negative polarity)
39
IOVDD1
I
Power supply 1 for digital I/O
40
TBAL
O
Tracking balance adjustment signal output
41
FBAL
O
Focus balance adjustment signal output
42
FE
I
Focus error signal input
43
TE
I
Tracking error signal input
44
ADPVCC
I
Voltage input for supply voltage monitor
45
RFENV
I
RF envelope signal input
46
LDON
O
Laser ON signal output
47
NRFDET
I
RF detectoion signal input
48
OFT
I
Off-track signal input
49
BDO
I
Dropout signal input
50
AVDD1
I
Power supply 1 for analog circuits
51
IREF
I
Analog reference current input
52
ARF
I
RF signal input
53
DSLF
O
DSL loop filter pin
54
PWMSEL
I
PWM output mode selection input Low: Direct High: 3-state
55
PLLF
O
PLL loop filter pin (for phase comparison)
56
PLLFO
O
PLL loop filter pin (for speed comparison)
57
AVSS1
I
Ground 1 for analog circuits
58
LOOUTL
O
L-ch audio output for line-out output
59
LOVSS1
I
Ground for line-out output
Содержание TCH-M900
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Страница 26: ... 2 22 IC505 AMC1117 BLOCK DIAGRAM ...
Страница 30: ... SCHEMATIC DIAGRAM MAIN SCHEMATIC DIAGRAM 2 27 2 28 ...
Страница 31: ...2 29 2 30 FRONT SCHEMATIC DIAGRAM ...
Страница 32: ...2 31 2 32 SCHEMATIC DIAGRAM CDP SCHEMATIC DIAGRAM ...
Страница 34: ...2 35 2 36 3 MAIN P C BOARD ...
Страница 35: ...2 37 2 38 4 CDP P C BOARD ...