3-41
Copyright © 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Symbol
Pin#
Type
Description
Configuration Interface Signals
SCL (SCANB)
22
DI, P/U
2-wire serial bus clock. Power down does not affect SCL. This pin
should be high when RSTB asserted for entering scan test mode.
SDA
21
DIO, P/U
2-wire serial bus data. Power down does not affect SDA.
CPUINT (A3)
23
DIO
Internal Interrupt.
This pin is a reset strap pin I
2
C device address. When RSTB goes
high, if this pin is high, then default I
2
C device address is 50h, else 40h.
RSTB
20
DI, P/U
Whole chip reset.
ADC Interface
ACB2
2
AI
Analog input 2 of channel 2
ACB1
3
AI
Analog input 1 of channel 2
ACB0
4
AI
Analog input 0 of channel 2
AY2
7
AI
Analog input 2 of channel 1
AY1
8
AI
Analog input 1 of channel 1
AY0
9
AI
Analog input 0 of channel 1
ACR2
12
AI
Analog input 2 of channel 0
ACR1
13
AI
Analog input 1 of channel 0
ACR0
14
AI
Analog input 0 of channel 0
VSI
18
DI
RGB Vertical synchronous input
HSI
19
DI
RGB Horizontal synchronous input
PLL and Slicer Interface
FILT
93
AI
PLL filler
VPLL
94
AI
PLL reference
SOYIN
97
AI
Sync on Y (of component) input
VREF
98
AI
Voltage reference
ITU-R656 Video-In Interface
VDT0~7
78~85
DI, P/D
Video data port of ITU-656 or 8-bit 601
VCLK
86
DI, P/D
Video clock of ITU-656 or 8-bit 601
CCIR-601 8-bits Video-In Interface
VDT0~7
78~85
DI, P/D
Video data port of 8-bit 601
VCLK
86
DI, P/D
Video clock of 8-bit 601
LODD/LVSYNC
87
DI, P/D
ITU-601 Odd or VSync input
LHREF/LHSYNC
88
DI, P/D
ITU-601 HREF(HDE) or HSync input
CCIR-601 16-bits Video-In Interface
VDT0~7
78~85
DI, P/D
Video data LSB port of 16-bit 601
VDT8~15
30, 34~31,
DIO, P/D
Video data MSB port of 16-bit 601 when panel is TTL 8 bits
29~27
VDT8~15
30, 34, 58~59
DIO, P/D
Video data MSB port of 16-bit 601 when panel is TTL 6 bits or sPanel
62~65
VCLK
86
DI, P/D
Video clock of 16-bit 601
LODD/LVSYNC
87
DI, P/D
ITU-601 Odd or VSync input
LHREF/LHSYNC
88
DI, P/D
ITU-601 HREF(HDE) or HSync input