3-40
Copyright © 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
2-2. Pin Description
Symbol
Pin#
Type
Description
Power Supplies
VDD25
17, 41, 66, 89
PWR
+2.5V digital core power supply
VD33
35, 48, 61, 73
PWR
+3.3V digital output power supply
GND
16, 39, 51, 60,
GND
Digital ground
70, 90
AVDDB
1
PWR
+3.3V analog power supply for ADC channel 2
AVDDG
6
PWR
+3.3V analog power supply for ADC channel 1
AVDDR
11
PWR
+3.3V analog power supply for ADC channel 0
AVDDP
91, 95
PWR
+3.3V analog power supply for PLL
AVDDDAC
99
PWR
+3.3V analog power supply for voltage slicer
AGNDB
5
GND
Anlog ground for ADC channel 2
AGNDG
10
GND
Anlog ground for ADC channel 1
AGNDR
15
GND
Anlog ground for ADC channel 0
GNDP
92, 96
GND
Anlog ground for PLL
GNDAC
100
GND
Anlog ground for voltage slicer
TTL Output Interface Signals
QE0~QE23
36~38, 40,
DIO, P/D
TTL Output Data :
42~47, 49, 50
1. for 8-bit panel: QE[23:16]=R-channel; QE[15:8]=G-channel;
52~59, 62~65
QE[7:0]=B-channel
2. for 6-bit panel: QE[17:12]=R-channel; Qe[11:6]=G-channel;
QE[5:0]=B-channel; and the QE[23:18] are reserved for other interfaces
HSO
67
DIO, P/D
Horizontal synchronization output control signal
VSO
68
DIO, P/D
Vertical synchronization output control signal
DEN
69
DIO, P/D
Horizontal output data enable signal
CLKO
71
DIO, P/D
Output dot clock
Timing Controller Interface Signls
POL
67
DIO, P/D
Source driver start pulse
STH1
68
DIO, P/D
Source driver start pulse
INVO/STH2
69
DIO, P/D
Source driver start pulse
LP
72
DIO, P/D
Latch pulse for column driver
GCLK
74
DIO, P/D
Gate driver clock
GOE
75
DIO, P/D
Gate driver output enable
STV1
76
DIO, P/D
Gate driver start pulse
STV2
77
DIO, P/D
Gate driver start pulse
Serial RGB Output Interface Signals
sRL
43
DIO, P/D
Right/Left control
sUD
44
DIO, P/D
Up/Down control
sHSo
45
DIO, P/D
sPanel_HSync
sVSo
46
DIO, P/D
sPanel_VSync
sDEN
47
DIO, P/D
sPanel_DEN
sD0~sD7
49~50, 52~57
DIO, P/D
sPanel_Data
CLKO
71
DIO, P/D
sPanel clock