1.
1. Circuit Block
Circuit Block Diagram
Diagram
DDR3 1866 X 16
X TAL
CI Slot
CI Slot
P_TS
P_TS
T/C Demod
IF (+/-)
DDR3 1866 X 16
(512MB X 2EA)
Air/
Cable
TUNER
(T2/C/A)
DDR3 1866 X 16
(512MB X 2EA)
X_TAL
24MHz
T2/C/S2 W/O AD
T2/C/S2 W/O AD
A
B
R
USB1
Analog Demod
SYSTEM EEPROM
(256Kb)
(T2/C/A)
TUNER
(S2)
DVB-S
DEMOD
(S2)
LNB
eMMC
P_TS
P_TS
I2C 1
OCP
E
A
R
(H)
CVBS
MAIN A di AMP
Mstar LM14
HDMI3 (MHL)
LNB
USB2
USB3
(2.0)
Video 4K@30p/2K@60p(Vx1 4 lane),
OSD FHD@60p(Vx1 2 lane)
(4GB)
I2S Out
Vx1
USB
2A
OCP
1.5A
(HDD)
Sil9617
LGE7411
MAIN Audio AMP
(NTP7514)
HDMI1 (HDCP2.2)
HDMI2 (ARC)
HDMI
MUX
I2S Out
I2C 4
IR / KEY
IR/KEY
HDCP2.2
R9531AN
Sil9617
LGE7411
Mux
H/P
AV/COMP
SCART
(IN/OUT)
CVBS/YPbPr
CVBS/RGB
WIFI/BT Combo
LOGO LIGHT(Ready)
SUB
ASSY
USB_WIFI
X_TAL
27MHz
Serial
Flash(4MB)
OPTIC
LAN
Sub Micom
(RENESAS
R5F100GEAFB)
X TAL
SPDIF OUT
ETHERNET
I2C 0
X_TAL
32.768KHz
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Содержание 49UB8200
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