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Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes.
Realtek
K3Lp
DDR3
2133
X
32
(512
MB
X
2EA)
Hyni
x
20n
m
DDR3
2133
X
32
(512
MB
X
2EA)
eMMC
(4GB)
Toshiba 15n
m
CI
S
lot
B-
CA
S
(JAPAN)
B-
CA
S
controller
SM
ARTCARD_I/F
USB2 (2
.0)
OCP
USB3 (2
.0)
HDMI
3
HDMI
2(ARC)
HDMI
1
Air/
Cable
DV
B-
S
LN
B
(DT1805)
REAR(H)
P_TS_O
UT
P_TS_IN
Sub
Mi
co
m
(RENESAS
R5F100GEA
FB)
X_
TAL
32.768KHz
I2
C 1
USB_WI
FI
X_
TAL
27MHz
Sub Assy
LAN
ETHERNET
SPDIF
AV/CO
MP
CVBS/YPbPr
SPDIF OU
T
H/P
AMP
RS-232
MAX323
MA
IN
A
udio
AM
P
(DTA2010M)
I2S
Out
I2
C
4
Vx
1 51P
(8 lane)
: LGD 60/65/70/75
Vx
1 / EP
I
I2
C 6
EPI
PM
IC
(SW
50B3A)
Level
shifter
M0
M1
B-
CA
S
I2
C 6
NVRAM
(256Kb)
I2
C 4
I2
C 2
EPI
bloc
k
HDMI
4 (EEPROM)
K3L only. (K3Lp
2
56
M
B
x
2e
a
SoC
)
USB1 (3
.0)
OCP
K3L only
IR
/ KEY(1Key
)
LOGO
LIGHT(Ready)
WI
FI/BT
Co
mb
o
MT
K
IC
HD
M
I 6
G
4
EPI
60P
x2
(3G, 6
lane) : LGD 43/49/55
CEDS
68Px
2
(1.5G, 12 lane)
:
BOE
T2/C/S2 NI
M t
uner
TS
TS
RF
IC
De
mo
de
(T
/C
/S/T2/S2)
BLOCK DIAGRAM
1. K3Lp Block Diagram (External)
Содержание 43UJ65 series
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