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Device parameters and interfaces
80
AMS 200
Leuze electronic
8
.2
SSI
8
.2.1
General information about the transmission procedure
Data communication of the SSI interface is based on differential transmission as used for
RS 422 interfaces. Transmission of the position value, beginning with the MSB (most signif-
icant bit), is thus synchronised with a clock cycle (CLOCK) specified by the control.
In the quiescent state both the clock line as well as the data line are at HIGH level. At the
first HIGH-LOW edge (point
➀
in figure 8.6) the data in the internal register are stored. Thus
it is ensured that the data cannot change during serial transmission.
When the next clock signal change from LOW to HIGH level (point
➁
transmission of the position value begins with the most significant bit (MSB). With each
successive change of the clock signal from LOW to HIGH level the next least-significant bit
is transmitted on the data line. After the least significant bit (LSB) has been output, the clock
signal switches from LOW to HIGH for one last time and the data line switches to LOW level
(end of transmission).
A monoflop retriggered by the clock signal determines the time span before the SSI interface
can be called for the next transmission. This results in the minimum pause time between two
successive clock cycles. If time t
m
= 20 µs has elapsed, the data line is returned to the quies-
cent level (HIGH) (point
➂
in figure 8.6). This signals completed data communication and
that the device is again ready for transmission.
Notice
!
If the off-cycle of data transmission is interrupted for longer than t
m
= 20 µs, the next cycle
will begin with a completely new transmission cycle with a newly calculated value.
If a new transmission cycle is started before time t
m
has elapsed, the previous value is out-
put again.
Attention
!
The SSI interface can only represent positive distance values. If negative output val-
ues are ascertained due to the offset or count direction, a zero value is output at the
SSI interface
!
In the event of a number overflow, all data bits are set to "1".