Lenze 9300 vector Series, Системное руководство

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Configuration
Use of funktion blocks
2−40
l
EDSVF9383V−EXT EN 2.0
4. AND2 is the third FB because it has a predecessor (see 3.)
5. Accordingly, the entries under C0465 are as follows:
– Position 10: AND1 10500
– Position 11: OR1 10550
– Position 12: AND2 10505
The example starts with position 10 because these positions have not been assigned with the default
setting.
The FBs need not be entered directly one after the other in the processing table. Empty positions are
permitted.
)
Note!
Other FBs may be entered between the FBs used in the example.
FBs which need not be entered into the processing table
The following signal sources are always executed. This is why they need not be entered into the
processing table:
l
AIF−IN
l CANx−IN
l
DIGIN
l
DIGOUT
l FCODE (all free codes)
l MCTRL
l
fixed signal sources (FIXED0, FIXED0%, etc.)
Frequent configuration errors
Error Cause Remedy
FB sends no output signal FB has not been entered into the processing
table under C0465 Enter FB into the processing table
FB only sends constant signals FB has been removed from the processing
table or overwritten Enter FB again into the processing table, if
necessary, under a different subcode (position)
The following FB does not receive the output
signal No connection between the FBs Build up connection (seen from the
subsequent FB’s view) under the configuration
code (CFG)
FB cannot be entered into the table under
C0465 Not enough process time available (see
C0466) Remove FBs which are not used, if any (e.g.
inputs and outputs which are not used)
With DC bus connections, some functions may
be transferred to other controllers, if
necessary
Controller transmits internal signals with
delay to the outputs FB processing order is not correct Adapt the processing table to the signal flow
under C0465