Lauterbach C2000, Руководство пользователя

Страница: 41 / 61

C2000 Debugger | 41
©
1989-2023
Lauterbach
<parameters> which are “Deprecated”
In the last years the chips and its debug and trace architecture became much more complex. Especially the
CoreSight trace components and their interconnection on a common trace bus required a reform of our
commands. The new commands can deal even with complex structures.
… BASE <address> This command informs the debugger about the start address of
the register block of the component. And this way it notifies the
existence of the component. An on-chip debug and trace
component typically provides a control register block which
needs to be accessed by the debugger to control this
component.
Example : SYStem.CONFIG ETMBASE APB:0x8011c000
Meaning: The control register block of the Embedded Trace
Macrocell (ETM) starts at address 0x8011c000 and is accessible
via APB bus.
In an SMP (Symmetric MultiProcessing) debug session you can
enter for the components BMC, CORE, CTI, ETB, ETF, ETM, ETR a
list of base addresses to specify one component per core.
Example assuming four cores: “SYStem.CONFIG COREBASE
0x80001000 0x80003000 0x80005000 0x80007000”.
COREBASE (old syntax: DEBUGBASE): Some cores e.g. Cortex-
A or Cortex-R do not have a fix location for their debug register
which are used for example to halt and start the core. In this case it
is essential to specify its location before you can connect by e.g.
SYStem.Up .
PERBASE and RAMBASE are needed for the RAM Trace Port
(RTP) which is available on some derivatives from Texas
Instruments. PERBASE specifies the base address of the core
peripheral registers which accesses shall be traced, RAMBASE
is the start address of RAM which accesses shall be traced. The
trace packages include only relative addresses to PERBASE and
RAMBASE.
For a list of possible components including a short description
see
Components and Available Commands .