Platform Manager
Development Kit
Technical Support
1-800-LATTICE (528-8423)
+1-503-268-8001
Done!
Congratulations! You have successfully demonstrated the Platform Manager
Development Kit. Please refer to the Platform Manager Development Kit User’s Guide
available on the Lattice web site at www.latticesemi.com/ptmdevkit for the following:
• Running advanced demos, including voltage monitoring, via I2C
• Details on additional development board features and operation
• Modifying and generating the demo program files from the PAC-Designer®
project sources
• Board schematics
• Gerber PCB layout artwork
Demo 5 – Test Two Push-buttons and Trimming/Margining
This demo shows the operation of the Closed Loop Trimming, and the ability of the
Platform Manager to have different voltage profiles for margining which are selectable on
the fly. There are three profiles used for this test. Profile 1 generates the target voltage
(e.g., 1.2V) and adjusts the output voltage up by 5%. Profile 2 adjusts the output voltage
down by 5%. Pressing either of the push-buttons shown below selects one of the profiles.
• Press and hold push-button PB_A_SW1.
- The voltage across the two pins of J8 will measure approximately 2.625V.
- The voltage across the two pins of J7 will measure approximately 1.26V.
• Release push-button PB_A_SW1.
• Press and hold push-button PB_B_SW2.
- The voltage across the two pins of J8 will measure approximately 2.375V.
- The voltage across the two pins of J7 will measure approximately 1.14V.
• Release push-button PB_B_SW2.
Demo 6 – Test Push-button S1 for Reset Function
Demo 6 illustrates the Platform Manager’s ability to sequence through a power-down
scenario, and in this case, restart the demo. When push-button S1 is depressed, the
DC-DC converter is powered down, followed by the LDO. The sequencer then returns
to the beginning of the demo and starts over.
• Move Slide Pots R19-R20 to the down position (center of the board). Press and
release push-button S1.
- The board will reset and the test will start over.
Copyright © 2013 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor
Corp., and Lattice (design), Platform Manager and PAC-Designer are either registered trademarks or trademarks
of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this
publication are for identification purposes only and may be trademarks of their respective companies.
QS009A
April 2013
