MachXO5T-NX-Development Board
Evaluation Board User Guide
FPGA-EB-02052-1.0
April 2023
Страница 1: ...MachXO5T NX Development Board Evaluation Board User Guide FPGA EB 02052 1 0 April 2023...
Страница 2: ...IS with all faults and associated risk the responsibility entirely of the Buyer Buyer shall not rely on any data and performance specifications or parameters provided herein Products sold by Lattice...
Страница 3: ...LFMXO5 100T Clock Sources 18 6 SGMII Ethernet Connections 19 7 PCIe Gold Finger 21 8 Optional SMA Headers 22 9 LPDDR4 Memory Controller Interface 24 10 Generating the Programming File 25 11 Programmin...
Страница 4: ...23 Figure 10 1 Radiant Software Open Project Dialog Box 25 Figure 10 2 Radiant Software Process Toolbar Initial State 25 Figure 10 3 Radiant Software State of the Processes Toolbar Completion 26 Figu...
Страница 5: ...Strapping Configuration 20 Table 6 3 SGMII Ethernet PHY1 Strapping Configuration 20 Table 6 4 PHY device VDD Power Supply Options 20 Table 7 1 Gold Finger Pin Connections 21 Table 8 1 Connections for...
Страница 6: ...n are subject to change without notice 6 FPGA EB 02058 1 0 Acronyms in This Document A list of acronyms used in this document Acronym Definition CMOS Complementary Metal Oxide Semiconductor DNI Do Not...
Страница 7: ...ludes the following MachXO5T NX Development Board pre loaded with the demo design 12 V AC DC Power adapter Mini USB cable Quick Start Guide The contents of this user guide include top level functional...
Страница 8: ...ice Two Gbe PHY RJ45 connectors with SGMII PHY support LPDDR4 up to 1066 Mbps 16 bits PCIe Gen2 x1 Edge Connector Optional SMA to support 1 PCIe Versa Headers bridge with Lattice ASC Demo Board to sup...
Страница 9: ...vice offers a variety of features and programmability that enhances Secure Control PLD functionality with Multiple Boot capabilities Its cryptographic engine supports user mode security features Along...
Страница 10: ...PMOD1 J16 VCCIO5 U3 J20 1 2V 1 8V 1 1V LDO U17 1 2V LDO U16 2 5V 2 5V VCCIO3 U3 1 1V PHY0 VDDP PHY1 VDDP U6 U7 PHY0 VDD U6 Reg0 out PHY0 U6 3 3V J28 PHY1 VDD U7 Reg1 out PHY1 U7 3 3V FTDI1 VCCIO U18 3...
Страница 11: ...ix on this board For an example VCCIO1 and VCCIO2 share the same three positions jumper J24 and short its Pin 1 and Pin 2 can bring the 3 3 V LDO output to both I O bank 1 and bank 2 For power consump...
Страница 12: ...hnology Devices International FTDI part U1 to convert USB to JTAG from port A or convert USB to I2 C from port B Using Detect Cable function with Radiant programming software installed you can detect...
Страница 13: ...and LFMXO5 100T JTAG port to make sure the FTDI fixed I O voltage can adapt with flexible voltage selection of bank 2 of the FPGA as shown in Figure 3 3 An eight pin header J1 Figure 3 4 allowing you...
Страница 14: ...push button with PROGRAMN reloads the bitstream from internal Flash when PROGRAMN_PORT function is enabled by software 3 2 I2 C Download Interface The USB hub on the PC can also detect the addition o...
Страница 15: ...arks of their respective holders The specifications and information herein are subject to change without notice FPGA EB 02058 1 0 15 Table 3 3 Download I2 C Connections Download I2C Net Name LFMXO5 10...
Страница 16: ...an then connect the mini USB to USB A cable from J19 to your PC The software select option FTUSB 0 is targeted for user JTAG and FTUSB 1 is targeted for UART that is mapped with port A and port B from...
Страница 17: ...e subject to change without notice FPGA EB 02058 1 0 17 4 2 Soft UART User Interface User FTDI Port B is also connected with GPIOs in Bank 0 directly You need allocate GPIOs for adaption with UART sig...
Страница 18: ...vice are not always on without some hardware configuration SMA clocks need source from external boards Refer to Table 5 1 for those clock utilization and enable conditions Table 5 1 Input Clock Option...
Страница 19: ...VI from Maxlinear as shown in Figure 6 1 Table 6 1 listed the signals from the FPGA interfacing with SGMII PHY devices LFMXO5 100T U3 PHY0 U6 PHY1 U7 RJ45 x2 J14 SGMII TX0 SGMII TX1 SGMII RX0 SGMII RX...
Страница 20: ...able 6 3 SGMII Ethernet PHY1 Strapping Configuration U7 Pin Number Configuration Item Description Logic Value in Default 1K Pull up Resistor 1K Pull down Resistor 37 PS_PHY_MADDR 0 0 R224 DNI R215 35...
Страница 21: ...EB 02058 1 0 21 7 PCIe Gold Finger MachXO5T NX Development Board supports 1 PCIe Gen2 as shown in Figure 7 1 The signal connections are listed in Table 7 1 Figure 7 1 Top Side of PCIe Edge Connector...
Страница 22: ...45 2S from Amphenol The signal mapping was shown as Table 8 1 Figure 8 1 SMA Interfacing for x1 Serdes RX and TX Table 8 1 Connections for SMA Serdes signal pair Reference Net Name LFMXO5 100T Ball Lo...
Страница 23: ...ders The specifications and information herein are subject to change without notice FPGA EB 02058 1 0 23 MachXO5T NX Development Board is also designed with a single end SMA clock header J10 as shown...
Страница 24: ...12M16D1 which is supported with 512 Meg 16 configurations This board is designed to use on die termination in default and reserved on board termination options Table 9 1 LPDDR4 Memory Controller Inter...
Страница 25: ...Board Rev A board can be downloaded from the Lattice website https www latticesemi com products developmentboardsandkits machxo5 nx development board To generate the JEDEC jed file 1 Open the Lattice...
Страница 26: ...ted at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change wi...
Страница 27: ...rogrammer can be used to program the JEDEC file to the MachXO5 NX embedded flash after the JEDEC data file is generated as shown in the Generating the Programming File section Radiant Programmer is in...
Страница 28: ...t to change without notice 28 FPGA EB 02058 1 0 Figure 11 2 Radiant Programmer Initial Opened 4 Click Run Scan Device to check the board through FTUSB 0 Port of embedded HW USBN 2B FTDI cable as shown...
Страница 29: ...ecifications and information herein are subject to change without notice FPGA EB 02058 1 0 29 Figure 11 4 Radiant Programmer Device Detected 6 Open the Device Properties dialog box by double click Ope...
Страница 30: ...6 Radiant Programmer Device Properties for FLASH Configuration Memory 7 Confirm the Device Operation options as follows Target Memory is FLASH Configuration Memory Port Interface is JTAG Access Mode i...
Страница 31: ...mes are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA EB 02058 1 0 31 Figure 11 7 Radiant Programm...
Страница 32: ...2 1 Versa Headers The board provides two headers J8 and J9 for expansion purpose Table 12 1 Versa J8 Header Pin Connections J8 Pin Number Net Name LFMXO5 100T Ball Location 1 GND 2 NC 3 EXPCON_2V5 4 E...
Страница 33: ...Name LFMXO5 100T Ball Location 1 HPE_RESOUT H14 2 GND 3 EXPCON_IO0 H15 4 EXPCON_IO1 H13 5 EXPCON_IO2 F15 6 EXPCON_IO3 H16 7 EXPCON_IO4 D16 8 EXPCON_IO5 F16 9 EXPCON_IO6 C17 10 EXPCON_IO7 A16 11 EXPCO...
Страница 34: ...AREF AREF PA03 L6 AR_AREF connection to AREF through R43 9 AR_SDA D20 PA22 SDA N5 Defaults to SDA function on Arduino ZERO Board It is optionally connected to SDA0 through R44 DNI 10 AR_SCL D21 PA23 S...
Страница 35: ...2 3 FPC Headers The board provides two 50 Pin FPC headers CN2 and CN3 for board signal extension Each header got 14 pairs of LVDS or SLVS signals for high speed data transmitter or receiver CN2 and CN...
Страница 36: ...SLVS_DP8 Y6 12 SLVS_DP20 N7 40 SLVS_DN8 Y7 11 SLVS_DN20 N8 41 GND 10 GND 42 SLVS_DP9 U7 9 SLVS_DP21 M12 43 SLVS_DN9 V7 8 SLVS_DN21 N12 44 GND 7 GND 45 SLVS_DP10 T7 6 SLVS_DP22 R11 46 SLVS_DN10 R7 5 SL...
Страница 37: ...G7 13 RASP_IO27 E6 14 GND 15 RASP_IO22 E5 16 RASP_IO23 E4 17 3 3V_RASP 18 RASP_IO24 E3 19 RASP_IO10 F7 20 GND 21 RASP_IO09 E2 22 RASP_IO25 F3 23 RASP_IO11 F2 24 RASP_IO08 F1 25 GND 26 RASP_IO07 G3 27...
Страница 38: ...tput high with pull up resistors If there is no pull up setup on the counterpart boards or internal GPIOs of FPGA you can add JP12 and JP13 to leverage FTDI s I2C pull up R33 and R34 for SCL0 SDA0 Not...
Страница 39: ...gistered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA EB 02058 1 0 39 Figure 12 1 Circuit Design for ADC0 Figure 12 2 Circ...
Страница 40: ...Switch Four LFMXO5 100T pins are connected to the four switches of SW1 as shown in the circuit design in Figure 13 1 The DIP switches are connected to logic level 0 when in the ON position as shown in...
Страница 41: ...ose applications At the same time SW2 can be used to trigger PCIE reset by adding JP10 jumper SW3 can be used to trigger the reset sequency of SGMII PHY devices after adding JP3 and JP5 jumpers SW4 ca...
Страница 42: ...NX Development Board Radiant 3 11 or later version Radiant Programmer 3 11 or later version 15 Storage and Handling Static electricity can shorten the life span of electronic components Observe these...
Страница 43: ...er brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA EB 02058 1 0 43 Techni...
Страница 44: ...e e S S Sc c ch h he e em m ma a at t ti i ic c c R R Re e ev v v o o o f f f S S Sh h he e ee e et t t T T Ti i it t tl l le e e L L La a at t tt t ti i ic c ce e e S S Se e em m mi i ic c co o on n...
Страница 45: ...A 1 1V DC DC 5V 1 5A 12V 0 5A 5V 3A 5V MiniUSB J11 MiniUSB J19 0 5A 5V PMOD Header1 Pg9 Pg9 Arduino Headers Pg9 Raspberry Pi Header Pg8 SGMII PHY0 RJ45 Pg8 Pg8 SGMII PHY1 RJ45 Pg8 Versa Header J8 Pg5...
Страница 46: ...e en n nt t t B B Bo o oa a ar r rd d d B B B 3 3 3 1 1 11 1 1 F F Fr r ri i id d da a ay y y F F Fe e eb b br r ru u ua a ar r ry y y 1 1 17 7 7 2 2 20 0 02 2 23 3 3 A A A U U US S SB B B t t to o o...
Страница 47: ...o o oa a ar r rd d d R R Re e ev v v P P Pr r ro o oj j je e ec c ct t t 1 1 1 0 0 0 M M Ma a ac c ch h hX X XO O O5 5 5 N N NX X X 1 1 10 0 00 0 0K K K D D De e ev v ve e el l lo o op p pm m me e en...
Страница 48: ...a a at t te e e S S Sc c ch h he e em m ma a at t ti i ic c c R R Re e ev v v o o o f f f S S Sh h he e ee e et t t T T Ti i it t tl l le e e L L La a at t tt t ti i ic c ce e e S S Se e em m mi i ic...
Страница 49: ...V C195 0 1uF 16V lpddr4 fbga200 x32 U9B DQ8_B AA11 DQ0_B AA2 DQ7_B AA4 DQ15_B AA9 DQ11_B U11 DQ3_B U2 DQ4_B U4 DQ12_B U9 DQS1_C_B V10 DQ10_B V11 DQ2_B V2 DQS0_C_B V3 DQ5_B V4 DQ13_B V9 DQS1_T_B W10 DQ...
Страница 50: ...M M Ma a ac c ch h hX X XO O O5 5 5 N N NX X X 1 1 10 0 00 0 0K K K D D De e ev v ve e el l lo o op p pm m me e en n nt t t B B Bo o oa a ar r rd d d B B B 7 7 7 1 1 11 1 1 F F Fr r ri i id d da a ay...
Страница 51: ...ac c ch h hX X XO O O5 5 5 N N NX X X 1 1 10 0 00 0 0K K K D D De e ev v ve e el l lo o op p pm m me e en n nt t t B B Bo o oa a ar r rd d d C C C 8 8 8 1 1 11 1 1 F F Fr r ri i id d da a ay y y F F...
Страница 52: ...S Sh h he e ee e et t t T T Ti i it t tl l le e e L L La a at t tt t ti i ic c ce e e S S Se e em m mi i ic c co o on n nd d du u uc c ct t to o or r r A A Ap p pp p pl l li i ic c ca a at t ti i io...
Страница 53: ...e ec c ct t t 1 1 1 0 0 0 M M Ma a ac c ch h hX X XO O O5 5 5 N N NX X X 1 1 10 0 00 0 0K K K D D De e ev v ve e el l lo o op p pm m me e en n nt t t B B Bo o oa a ar r rd d d B B B 1 1 10 0 0 1 1 11...
Страница 54: ...oa a ar r rd d d R R Re e ev v v P P Pr r ro o oj j je e ec c ct t t 1 1 1 0 0 0 M M Ma a ac c ch h hX X XO O O5 5 5 N N NX X X 1 1 10 0 00 0 0K K K D D De e ev v ve e el l lo o op p pm m me e en n n...
Страница 55: ...8 C131 C132 C133 C134 C135 C136 C140 C141 C142 C144 C145 C146 C147 C148 C149 C150 C151 C153 C155 C178 C179 C180 C181 C182 C183 C184 C185 C214 C215 C225 C226 C227 C228 C229 C230 C231 C233 C236 C239 C24...
Страница 56: ...T C0402 GCM155R 71C224KE 02D Murata CAP CER 0 22UF 16V X7R 0402 13 C88 C102 C104 C105 C106 C107 C108 C143 8 10uF C1206 CL31B106 KBHNNNE Samsung CAP CER 10UF 50V X7R 1206 14 C89 C91 C109 C110 C111 C112...
Страница 57: ...11 JP12 JP13 JP14 JP15 JP16 JP17 JP18 JP 19 JP20 JP21 JP22 JP23 JP24 JP25 JP26 JP27 27 JUMPER Header_ 1x2 86140002 1YO2LF Amphenol CONN HEADER VERT 2POS 2 54MM 28 J1 J18 2 Header 1x8 hdr_amp _87220_ 8...
Страница 58: ...3S AAN RC Sullins CONN HEADER VERT 3POS 2 54MM 42 L1 L2 L3 L4 L5 L6 L7 L8 L12 L13 L14 L15 L16 L17 L18 L19 L20 L22 L23 L24 20 600ohm 500mA fb0603 BLM18KG 601SN1D Murata FERRITE BEAD 600 OHM 0603 1LN 43...
Страница 59: ...4 R45 R59 R60 R78 R79 R84 R85 R86 R87 R88 R92 R94 R96 R130 R146 R147 R159 22 0 R0603 DNI 55 R53 R107 R108 3 23 7K DNI R0603 DNI 56 R54 R70 R71 R72 R109 R110 R144 R162 R163 R241 R242 R244 R245 R249 R25...
Страница 60: ...402 DNI 69 R167 R195 R246 R251 4 100 R0402 DNI 70 R238 R239 2 49 9E R0402 RC0402FR 0749R9L Yageo RES SMD 49 9 OHM 1 1 16W 0402 71 R252 1 150 R0201 RC0201FR 07150RL Yageo RES 150 OHM 1 1 20W 0201 72 R2...
Страница 61: ...0154005 DRT Littelfuse FUSE BRD MNT 5A 125VAC VDC 2SMD 86 U11 U12 2 BD9D321E FJ HTSOP_8 _BD9D32 1 BD9D321E FJ E2 Rohm IC REG BUCK ADJ 3A 8HTSOP J 87 U13 1 NCV1117S T25T3G sot223_4 p NCV1117S T25T3G O...
Страница 62: ...tticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice...
Страница 63: ...te M20 get_ports LED 6 ldc_set_location site M19 get_ports LED 7 DIP Switch Connections ldc_set_location site V2 get_ports DIPSW 0 ldc_set_location site V3 get_ports DIPSW 1 ldc_set_location site W2 g...
Страница 64: ...e W4 get_ports slvs_data 26 ldc_set_location site W5 get_ports slvs_data 27 LPDDR4 DQS GROUP 0 ldc_set_location site N18 get_ports ddr_dq_io 0 ldc_set_location site N20 get_ports ddr_dq_io 1 ldc_set_l...
Страница 65: ...19 get_ports PMOD0_4 ldc_set_location site K19 get_ports PMOD0_5 ldc_set_location site L17 get_ports PMOD0_6 ldc_set_location site L20 get_ports PMOD0_7 ldc_set_location site M18 get_ports PMOD0_8 PMO...
Страница 66: ...dc_set_location site H15 get_ports EXPCON_IO0 ldc_set_location site H13 get_ports EXPCON_IO1 ldc_set_location site F15 get_ports EXPCON_IO2 ldc_set_location site H16 get_ports EXPCON_IO3 ldc_set_locat...
Страница 67: ...location site G18 get_ports HPE_CARDSEL Aardvark Header Connections ldc_set_location site M7 get_ports AK_SCL ldc_set_location site M8 get_ports AK_SDA ldc_set_location site N1 get_ports AK_MISO ldc_s...
Страница 68: ...FPGA EB 02058 1 0 Appendix D MachXO5T NX Development Board Errata As shown in Appendix A MachXO5T NX Development Board Schematics Page3 of the Schematics USB to Hard JTAG I F Pin 1 of J1 and Pin 15 o...
Страница 69: ...semi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA...
Страница 70: ...d disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein...
Страница 71: ...www latticesemi com...
