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MachXO5-NX Development Board
Evaluation Board User Guide

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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-EB-02052-1.0

Figure A.7. High Speed Header (BANK5/6)

NOTE : PLACE ALL THE TERMINATION

RESISTORS ON TOP SIDE AND CLOSE

TO THE U3

LVDS RX TERMINATION RESISTORS

Note :

1) Match length within pair as well as other pairs with +/- 5% tolerence

2)Differential impedance should be 100 Ohms and 50 Ohms as a single ended signals

3)All the power rails should be capable of carrying 1A current

Note : Speed of the bus, < 2.5ps skew for pairs and

across the bus, traces should be 100 Ohms

Trace match LVDSI* pins between P and N channels as

well as individual pairs.

CrossLink Headers

CH0_DCK_P

CH0_DCK_N

CH0_DATA0_N

CH0_DATA0_P

CH0_DATA1_P

CH0_DATA1_N

CH2_DATA1_N

CH2_DATA1_P

CH1_DCK_P

CH1_DCK_N

CH0_DATA3_P

CH0_DATA3_N

CH0_DATA2_N

CH0_DATA2_P

CH1_DATA0_N

CH1_DATA1_P

CH1_DATA0_P

CH1_DATA1_N

CH1_DATA2_N

CH1_DATA2_P

CH2_DATA0_P

CH2_DATA0_N

CH2_DCK_N

CH2_DCK_P

CH1_DATA3_N

CH1_DATA3_P

CH3_DATA1_N

CH3_DATA1_P

CH3_DCK_N

CH3_DCK_P

CH3_DATA0_N

CH3_DATA0_P

FX_MOSI

FX_SN
FX_SCLK

FX_MISO

CH1_DCK_P

CH1_DCK_N

CH1_DATA0_P

CH3_DATA0_N

CH1_DATA0_N

CH1_DATA2_P

FX_RESETN

CH1_DATA2_N

CH3_DCK_N

CH1_DATA3_N

CH1_DATA3_P

CH1_DATA1_N

CH3_DATA0_P

CH1_DATA1_P

CH3_DATA1_N

CH3_DATA1_P

CH3_DCK_P

CH0_DATA2_P

CH0_DATA1_P

CH0_DCK_P

CH0_DCK_N

CH0_DATA0_P
CH0_DATA0_N

CH0_DATA2_N

CH2_DATA0_P

CH2_DATA0_N

CH2_DCK_P
CH2_DCK_N

CH0_DATA1_N

CH0_DATA3_P

CH0_DATA3_N

CH2_DATA1_P

CH2_DATA1_N

FX_RESETN

SDA2

SCL2

SDA1
SCL1

SCL2

SDA2

SCL1

SDA1

FX_MOSI
FX_MISO

FX_SN
FX_SCLK

SGMII_MDIO_DATA

SGMII_MD1_N

SGMII_MD2_P

SGMII_MD1_P

SGMII_MD3_P
SGMII_MD3_N

SGMII_MD0_P

SGMII_MD0_N

SGMII_MD2_N

SGMII_INT

SGMII_PHY_SIP
SGMII_PHY_SIN

SGMII_CLK_OUT

SGMII_MDIO_CLK

SGMII_RST_N

SGMII_PHY_SOP
SGMII_PHY_SON

SGMII_PHY_COP
SGMII_PHY_CON

SGMII_LED2
SGMII_LED1

SGMII_LED0

SGMII_XO

SGMII_XI

SGMII_XO

SGMII_XI

SGMII_MD1_N

SGMII_MD2_P

SGMII_MD1_P

SGMII_MD3_N

SGMII_MD3_P

SGMII_MD2_N

SGMII_MD0_P
SGMII_MD0_N

SGMII_LED0

SGMII_LED1

SGMII_LED2

DPHY0_FSYNC

DPHY0_CKP

DPHY0_CKN

DPHY0_DP0

DPHY0_DN0

DPHY0_DP1

DPHY0_DN1

DPHY0_DP2

DPHY0_DN2

DPHY0_DP3

DPHY0_DN3

DPHY0_SDA

DPHY0_SCL

DPHY0_CLK

DPHY0_RST

DPHY0_CKP
DPHY0_CKN

SGMII_FPGA_CLKP

SGMII_FPGA_CLKN

SGMII_PHY_COP

SGMII_PHY_CON

SGMII_PHY_SOP

SGMII_PHY_SON

SGMII_FPGA_RXP

SGMII_FPGA_RXN

SGMII_FPGA_TXP

SGMII_FPGA_TXN

SGMII_PHY_SIP

SGMII_PHY_SIN

SDA1

SDA2

SCL1

SCL2

FX_SN

FX_MOSI

FX_MISO

FX_SCLK

FX_RESETN

DPHY0_DP3

DPHY0_DN3

DPHY0_DP1

DPHY0_DN1

DPHY0_DP0
DPHY0_DN0

DPHY0_DP2

DPHY0_DN2

CH1_DCK_P

CH1_DCK_N

CH3_DCK_N

CH3_DCK_P

CH1_DATA1_N

CH1_DATA1_P

CH1_DATA3_P

CH1_DATA3_N

CH1_DATA0_N

CH1_DATA0_P

CH1_DATA2_P
CH1_DATA2_N

SGMII_FPGA_CLKP

SGMII_FPGA_CLKN

SGMII_FPGA_RXP
SGMII_FPGA_RXN

SGMII_FPGA_TXP

SGMII_FPGA_TXN

CH0_DCK_P

CH0_DCK_N

CH2_DCK_P
CH2_DCK_N

CH0_DATA0_N

CH0_DATA0_P

CH0_DATA2_P
CH0_DATA2_N

CH0_DATA1_P
CH0_DATA1_N

CH0_DATA3_N

CH0_DATA3_P

CH2_DATA0_P

CH2_DATA0_N

CH2_DATA1_N

CH2_DATA1_P

CH3_DATA0_N

CH3_DATA0_P

CH3_DATA1_P

CH3_DATA1_N

SGMII_INT

SGMII_MDIO_DATA

SGMII_MDIO_CLK

SGMII_RST_N

DPHY0_SDA
DPHY0_SCL

DPHY0_FSYNC

DPHY0_CLK

DPHY0_RST

SGMII_CLK_OUT

+12V

+1.8V

+12V

+3.3V

+5.0V

+12V

+3.3V

+5.0V

+1.8V

+12V

+3.3V +1.8V

+5.0V +3.3V +1.8V

+5.0V

VCCIO5

VCCIO6

SGMII_VDDIO

SGMII_PHY_D1V8

+2.5V

SGMII_VDDIO

+2.5V

+3.3V

VCCIO5

VCCIO6

VRAM

CVDD

+2.8V

VCCA_1V_PHY

+1.8V

+1.0V

VRAM

VCCA_1V_PHY

+2.5V

SGMII_PHY_D1V8

SGMII_VDDIO

SDA1

[8]

SDA2

[8]

SCL2

[8]

SCL1

[8]

FX_MOSI

[8]

FX_SN

[8]

FX_SCLK

[8]

FX_MISO

[8]

FX_RESETN

[8]

SGMII_INT

[8]

SGMII_MDIO_DATA

[8]

SGMII_MDIO_CLK

[8]

SGMII_RST_N

[8]

DPHY0_SDA

[9]

DPHY0_SCL

[9]

DPHY0_CLK

[9]

DPHY0_FSYNC

[9]

DPHY0_RST

[9]

SGMII_CLK_OUT

[8]

Date:

Size

Schematic Rev

o f

Sheet

Title

Lattice Semiconductor Applications

Email: [email protected]

Phone (503) 268-8001 -or- (800) LATTICE

Board Rev

Project

1.0

MachXO5-NX Development Board

Thursday, January 13, 2022

High Speed Heads(BANK5/6)

Date:

Size

Schematic Rev

o f

Sheet

Title

Lattice Semiconductor Applications

Email: [email protected]

Phone (503) 268-8001 -or- (800) LATTICE

Board Rev

Project

1.0

MachXO5-NX Development Board

Thursday, January 13, 2022

High Speed Heads(BANK5/6)

Date:

Size

Schematic Rev

o f

Sheet

Title

Lattice Semiconductor Applications

Email: [email protected]

Phone (503) 268-8001 -or- (800) LATTICE

Board Rev

Project

1.0

MachXO5-NX Development Board

Thursday, January 13, 2022

High Speed Heads(BANK5/6)

D13

Red

R38

2.2K

DNI

C146 100nF

C181

1uF

R56
100

DNI

C175

1uF

C158

1uF

R54
100

DNI

R49
100

DNI

C18

18pF

C147 100nF

R53
100

DNI

MachXO5-NX

U3F

VCCIO5

T12

VCCIO5

V14

PB48B/ ADC_CN14/BDQ42

N12

PB48A/ ADC_CP14/BDQ42

N13

PB52A/ ADC_CP11/BDQ54

P13

PB40B/ COMP1IN/PCLKC5_0/BDQ42

R11

PB52B/ ADC_CN11/BDQ54

R13

PB58B/ PCLKC5_3/LRC_GPLL0T_MFGOUT2/BDQ54

R14

PB40A/ COMP1IP/PCLKT5_0/BDQ42

T11

PB50B/ COMP3IN/BDQ54

T13

PB58A/ PCLKT5_3/LRC_GPLL0T_MFGOUT1/BDQ54

T14

PB38B/ ADC_CN4/BDQ42

U11

PB44B/ COMP2IN/BDQ42

U12

PB50A/ COMP3IP/BDQ54

U13

PB56B/ ADC_CN15/BDQ54

U14

PB38A/ VREF5_1/ADC_CP4/BDQ42

V11

PB44A/ COMP2IP/BDQ42

V12

PB56A/ ADC_CP15/BDQ54

V13

PB42B/ PCLKC5_1/ADC_CN8/BDQSN42

W11

PB46B/ PCLKC5_2/ADC_CN13/BDQ42

W12

PB54B/ ADC_CN12/BDQSN54

W13

PB60B/ LRC_GPLL0C_IN/VREF5_2/ATB_SENSE/BDQ54

W14

PB42A/ PCLKT5_1/ADC_CP8/BDQS42

Y11

PB46A/ PCLKT5_2/ADC_CP13/BDQ42

Y12

PB54A/ ADC_CP12/BDQS54

Y13

PB60A/ LRC_GPLL0T_IN/ATB_FORCE/BDQ54

Y14

C184

0.1uF

MMBT3904

FB12

MPZ1005S121CT000

C182

0.1uF

R158

1M Ohm

C159

1uF

R89

100

R166
1K

DP83867ERGZT

TX_D3

TX_D2

TX_D1/SGMII_SIP

TX_D0/SGMII_SIN

GTX_CLK

VDDIO

VDD1P0

RX_CLK

RX_D0/SGMII_COP

RX_D1/SGMII_CON

RX_D2/SGMII_SOP

RX_D3/SGMII_SON

TX_CTRL

RX_CTRL

GPIO_0

GPIO_1

VDDIO

VDD1P0

RESET

INT/PWDN

LED_2

LED_1

LED_0

VDDA1P8

TD_P_A

TD_M_A

VDDA2P5

TD_P_B

TD_M_B

VDD1P0

TD_P_C

TD_M_C

VDDA2P5

TD_P_D

TD_M_D

RBIAS

VDDA1P8

MDC

MDIO

CLK_OUT

VDDIO

JTAG_CLK

JTAG_TDO

JTAG_TMS

JTAG_TDI

VDD1P0

C183

0.1uF

R205

100

C162

0.1uF

C149 100nF

C160

1uF

C44

0.1uF

JP3

PHY_PD

R57
100

DNI

C166

10uF

C24

100nF

C43

0.1uF

R219

2.2K

C163

0.1uF

C161

1uF

R77

2.2K

C167

1uF

C148 100nF

R60
100

DNI

FB1

MPZ1005S121CT000

Hirose - FX12 - 40 Pos

DNI

CH1_DCK_P

CH1_DCK_N

GND

CH1_DATA0_P

CH1_DATA0_N

GND

CH1_DATA2_P

CH1_DATA2_N

GND

SCLK

PWR_12_0V

SDA1

SCL1

GND

CH3_DATA0_P

CH3_DATA0_N

GND

CH3_DCK_P

CH3_DCK_N

PWR_12V

RESETN

PWR_5-0V

CH1_DATA1_P

CH1_DATA1_N

PWR_3-3V

CH1_DATA3_P

CH1_DATA3_N

PWR_1-8V

MOSI

MISO

PWR_1-8V

GND

PWR_3-3V

CH3_DATA1_P

CH3_DATA1_N

PWR_5-0V

SDA

SCL

Shield1

Shield2

Shield3

Shield4

Shield5

Shield6

R61
100

DNI

R220

2.2K

C26

100nF

C176

0.1uF

C168

1uF

R76

2.2K

C164

0.1uF

C157

10uF

C22

100nF

R221

2.2K

R167
1K

C177

0.1uF

R124

10K

C169

10uF

R64
100

DNI

R32

11K

C150 100nF

R52
100

DNI

C21

100nF

R59
100

DNI

D15

Red

C165

0.1uF

C170

0.1uF

C25

100nF

R51
100

DNI

MachXO5-NX

U3G

VCCIO6

PB2A/ VREF6_1/BDQ6

PB10A/ CDR_RXP1/ADC_CP3/BDQ6

PB14A/ CDR0_TESTP/ADC_CP5/BDQ18

N10

PB36A/ BDQ18

N11

PB2B/ BDQ6

PB10B/ CDR_RXN1/ADC_CN3/BDQ6

PB14B/ CDR0_TESTN/ADC_CN5/BDQ18

P10

PB36B/ VREF6_2/BDQ18

P11

PB16A/ CDR1_TESTP/ADC_CP7/BDQ18

R10

PB4A/ BDQ6

PB16B/ CDR1_TESTN/ADC_CN7/BDQ18

T10

PB4B/ BDQ6

PB12A/ PCLKT6_2/ADC_CP2/COMP3P/BDQ6

PB32A/ ADC_CP9/BDQ18

U10

PB12B/ PCLKC6_2/ADC_CN2/COMP3N/BDQ6

PB32B/ ADC_CN9/BDQ18

V10

PB6A/ PCLKT6_0/CDR_RXP0/ADC_CP0/COMP1P/BDQS6

PB8A/ PCLKT6_1/ADC_CP1/COMP2P/BDQ6

PB18A/ ADC_CP6/BDQS18

PB34A/ PCLKT6_3/ADC_CP10/BDQ18

W10

PB6B/ PCLKC6_0/CDR_RXN0/ADC_CN0/COMP1N/BDQSN6

PB8B/ PCLKC6_1/ADC_CN1/COMP2N/BDQ6

PB18B/ ADC_CN6/BDQSN18

PB34B/ PCLKC6_3/ADC_CN10/BDQ18

Y10

C151 100nF

C23

100nF

D14

Red

C39

10uF

R63
100

DNI

R68

DNI

R129

10K

C171

0.1uF

MMBT3904

J27

24580403

NC1

CLK_N

CLK_P

DGND

DATA3_N

DATA3_P

DGND

DATA1_N

DATA1_P

DGND

DATA0_N

DATA0_P

DGND

DATA2_N

DATA2_P

DGND

AF_GND

AF_VDD2V8

NC2

MCLK

NC3

SDA

SCL

RESET

VDD1.05V

DVDD1V8

DGND

AGND

AVDD2V8

AGND

R67

DNI

C185

1uF

C40

0.1uF

C178

10uF

J14

7498111001-RJ45

R36

100

R75

Hirose - FX12 - 40 Pos

DNI

CH0_DCK_P

CH0_DCK_N

GND

CH0_DATA0_P

CH0_DATA0_N

GND

CH0_DATA2_P

CH0_DATA2_N

GND

SCLK

PWR_12V

SDA1

SCL1

GND

CH2_DATA0_P

CH2_DATA0_N

GND

CH2_DCK_P

CH2_DCK_N

PWR_12-0V

RESETN

PWR_5-0V

CH0_DATA1_P

CH0_DATA1_N

PWR_3-3V

CH0_DATA3_P

CH0_DATA3_N

PWR_1-8V

MOSI

MISO

PWR_1-8V

GND

PWR_3-3V

CH2_DATA1_P

CH2_DATA1_N

PWR_5-0V

SDA

SCL

Shield1

Shield2

Shield3

Shield4

Shield5

Shield6

C27

100nF

C173

1uF

MMBT3904

25 MHz

ABM3-25

R58
100

DNI

R65

2.49K

R165
1K

C19

18pF

R50
100

DNI

C41

0.1uF

C156

10uF

C179

1uF

C172

10uF

R233

4.7k

R55
100

DNI

FB6

MPZ1005S121CT000

FB10

MPZ1005S121CT000

R66

2.49K

R62
100

DNI

C42

10uF

C28

18pF

C180

10uF

R203

100

C174

10uF

C20

100nF

R234

4.7k

Содержание MachX05-NX

Страница 1: ...MachXO5 NX Development Board Evaluation Board User Guide FPGA EB 02052 1 0 June 2022 ...

Страница 2: ...S IS with all faults and associated risk the responsibility entirely of the Buyer Buyer shall not rely on any data and performance specifications or parameters provided herein Products sold by Lattice have been subject to limited testing and it is the Buyer s responsibility to independently determine the suitability of any products and to test and verify the same No Lattice products should be used...

Страница 3: ...Soft UART User Interface 15 5 MachXO5 25 Clock Sources 17 6 SGMII Ethernet Connections 18 7 HyperRAM 20 8 Headers and Test Connections 21 8 1 Versa Headers 21 8 2 Arduino Board GPIO Headers 23 8 3 FX12 Headers 24 8 4 Aardvark Header DNI 26 8 5 Raspberry Pi Board GPIO Header 26 8 6 PMOD Headers 27 8 7 MIPI Camera Header 28 8 8 User I2 C Interface 29 8 9 ADC and Potentiometer 30 8 10 Other Test Poin...

Страница 4: ...13 Figure 3 4 JTAG Test Header 13 Figure 3 5 I2 C Programming Mode 14 Figure 4 1 JTAG UART User Interfacing 15 Figure 5 1 Onboard Clock Resources 17 Figure 8 1 MIPI Camera Sensor Interface 28 Figure 8 2 MIPI Camera Sensor Power Supply Header 29 Figure 8 3 Circuit Design for ADC0 30 Figure 8 4 Circuit Design for ADC1 31 Figure 8 5 Trimmer Wiper Description 31 Figure 9 1 Four Position DIP Switch Cir...

Страница 5: ...tions 17 Table 6 1 SGMII Ethernet PHY Connections 18 Table 7 1 HyperRAM Pin Mapping 20 Table 8 1 Versa J8 Header Pin Connections 21 Table 8 2 Versa J9 Header Pin Connections 22 Table 8 3 Arduino J2 Pin Connections 23 Table 8 4 Arduino J3 Pin Connections 23 Table 8 5 Arduino J4 Pin Connections 23 Table 8 6 Arduino J5 Pin Connections 24 Table 8 7 FX12 U4 Header Pin Connections 24 Table 8 8 FX12 U5 H...

Страница 6: ...s of their respective holders The specifications and information herein are subject to change without notice 6 FPGA EB 02052 1 0 Acronyms in This Document A list of acronyms used in this document Acronym Definition CMOS Complementary Metal Oxide Semiconductor DNI Do Not Install FTDI Future Technology Devices International GPIO General Purpose Input Output I2C Inter Integrated Circuit LDO Low Dropo...

Страница 7: ...llowing MachXO5 NX Development Board pre loaded with the demo design 12 V AC DC Power adapter Mini USB cable Quick Start Guide The contents of this user guide include top level functional descriptions of the various portions of the development board descriptions of the onboard headers diodes and switches and a complete set of schematics 1 1 MachXO5 NX Development Board Along with the MachXO5 25 de...

Страница 8: ... Appendix D for the board revision information HyperRAM upto 166MHz x16 bits Versa Headers bridge with Lattice ASC Demo Board to support L ASC10 General Purpose Input Output GPIO interface with PMOD Arduino and Raspberry Pi boards USB B connection for device programming with JTAG and Inter Integrated Circuit I2 C utility Additional USB B connection for user with Soft JTAG and UART utility 7 Segmen...

Страница 9: ...t Board features the MachXO5 25 in a 400 ball caBGA package This device offers a variety of features and programmability that enhances Secure Control PLD functionality with Multiple Boot capabilities Its cryptographic engine supports user mode security features Along with the cryptographic engine numerous system functions are included such as two PLLs and 432 kbits of embedded RAM plus hardened im...

Страница 10: ...3V VCCIO8 U3 J23 3 3V 3 3V VCCIO7 U3 J22 3 3V 1 8V VCCIO4 U3 J29 1 2V 2 5V VCCIO6 U3 J21 1 2V 1 8V VCCIO5 U3 J20 1 8V 1 2V 5V VCCIO9 U3 1 8V VCCAUX VCCAUXA VCCAUX H VCCADC U3 1 8V FX12 Headers U4 U5 Power Jack J17 12V 5V 3 3V 1 8V HyperRAM U6 U9 JTAG J1 PMOD J15 JTAG J18 PMOD J16 SMGIIVDDIO U7 PMOD J28 30 pin Header J27 2 8V Figure 2 1 Board Power Supply The onboard 5 V power regulator U11 provide...

Страница 11: ...2 share the same three positions jumper J25 and short its Pin 1 and Pin 2 can bring the 3 3 V LDO output to both I O bank 0 and bank 2 For power consumption evaluation this board facilitate some two position jumpers with 1 Ω sense resistors to measure the voltage drop on each power rail then the supply current can be calculated Table 2 2 MachXO5 25 IO Bank Power Rails Stuff MachXO5 25 Power U3 Jum...

Страница 12: ...nsuring FTDI reset control jumper JP9 is not populated as default The software select option FTUSB 0 is dedicate for hard JTAG and FTUSB 1 is dedicate for hard I2 C which is mapping with port A and port B from hardware perspective as shown in Figure 3 2 Mini USB J11 USB FT2232H U1 Port A Port B MachXO5 NX U3 Level Shift U14 rst JP9 GND FTDI_SCL FTDI_SDA SCL0 SDA0 JP12 JP13 TDI TCK TMS TDO NX_TDI N...

Страница 13: ...cations and information herein are subject to change without notice FPGA EB 02052 1 0 13 output tri state mode avoiding multi drivers on those shared signals The JTAG connections between J1 and MachXO5 25 are listed in Table 3 1 Figure 3 3 Level Shift for JTAG Download Interface Figure 3 4 JTAG Test Header Table 3 1 Config JTAG Connections J1 Pin Number JTAG Net Name MachXO5 25 Ball Location for J...

Страница 14: ...ion on Config FTDI Port B and you can select the port FTUSB 1 on the programmer interface for the accessing from Config FTDI Port B to the MachXO5 25 dedicated I2 C download port Figure 3 2 that is named as FTDI_SDA FTDI_SCL with 2 2 kΩ pull up resistor each The Diode D21 is inserted to support I2 C clock stretching mode Figure 3 5 details the design of Config FTDI Port B for dedicated I2 C downlo...

Страница 15: ... and FTUSB 1 is targeted for UART that is mapped with port A and port B from hardware perspective Mini USB J19 USB FT2232H U18 Port A Port B MachXO5 NX U3 rst JP8 GND RS232_RX_TTL UTDI UTCK UTMS UTDO User JTAG Header J18 RS232_TX_TTL Figure 4 1 JTAG UART User Interfacing 4 1 Soft JTAG User Interface User FTDI Port A is connected with GPIOs in Bank 1 directly but you need allocate GPIOs for adaptio...

Страница 16: ...oduct names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice 16 FPGA EB 02052 1 0 Table 4 2 Soft UART Connections FTDI Signal UART Net Name MachXO5 25 Ball Location for Port A UBDBUS0 RS232_RX_TTL B11 UBDBUS1 RS232_TX_TTL B12 UBDBUS2 RTSn B13 UBDBUS3 CTSn B14 UBDBUS4 DTRn B15 UBDBUS5 DSRn B16 UBDBUS6 ...

Страница 17: ..._OSC J11 J19 USB USB Clock Generator SMA Figure 5 1 Onboard Clock Resources You need take care that only 27 MHz and 125 MHz clocks are active in default after board power up Both 12 MHz clocks from the FT2232H FTDI U1 and U18 device are not always on without some hardware configuration 25 MHz of SGMII and external clock need source from other devices Refer to Table 5 1 for those clock utilization ...

Страница 18: ...SGMII_MD3_P To RJ45 12 RBIAS Pull down to GND 13 VDDA1P8 SGMII_PHY_D1V8 1 8 V Power 14 XO SGMII_XO 25 MHz Crystal Output 15 XI SGMII_XI 25 MHz Crystal Input 16 MDC SGMII_MDIO_CLK U1 Optional pull up to VDDIO 17 MDIO SGMII_MDIO_DATA U2 Pull up to VDDIO 18 CLK_OUT SGMII_CLK_OUT T7 With 22 Ω debounce resistor 19 VDDIO SGMII_VDDIO VCCIO7 selectable 20 JTAG_CLK Pull down to GND 21 JTAG_TDO Pull up to V...

Страница 19: ...ks of their respective holders The specifications and information herein are subject to change without notice FPGA EB 02052 1 0 19 U7 Pin Number U7 Signal Name Net Name MachXO5 25 Ball Location Application Notes 43 RESET SGMII_RST_N T6 Default Pull down 44 INT PWDN SGMII_INT T5 Default pull up Shunt JP3 to pull down 45 LED_2 SGMII_LED_2 Drive Red LED D15 46 LED_1 SGMII_LED_1 Drive Red LED D14 47 L...

Страница 20: ...able 7 1 HyperRAM Pin Mapping Cypress HyperRAM in 24 Ball FBGA Connection for HyperRAM0 U6 Connection for HyperRAM1 U9 Symbol Name Ball Location Net Name MachXO5 25 Ball Location Net Name MachXO5 25 Ball Location RFU1 A2 RFU2 A5 CS A3 HR0_CS J3 HR1_CS G6 RESET A4 HR_RST D2 HR_RST D2 CK B1 HR0_CKN J1 HR1_CKN K4 CK B2 HR0_CK J2 HR1_CK K5 VSS B3 GND GND VSSQ C1 GND GND VSSQ E5 GND GND VCC B4 VRAM VRA...

Страница 21: ...8 1 Versa Headers The board provides two headers J8 and J9 for expansion purpose Table 8 1 Versa J8 Header Pin Connections J8 Pin Number Net Name MachXO5 25 Ball Location 1 GND 2 NC 3 EXPCON_2V5 4 EXPCON_IO29 C20 5 EXPCON_IO30 H14 6 EXPCON_IO31 G14 7 EXPCON_IO32 H15 8 EXPCON_IO33 G18 9 EXPCON_IO34 H16 10 EXPCON_IO35 G19 11 EXPCON_IO36 H20 12 EXPCON_IO37 H19 13 EXPCON_IO38 J17 14 EXPCON_IO39 J18 15...

Страница 22: ...9 Pin Number Net Name MachXO5 25 Ball Location 1 HPE_RESOUT F5 2 GND 3 EXPCON_IO0 D3 4 EXPCON_IO1 E4 5 EXPCON_IO2 C3 6 EXPCON_IO3 C2 7 EXPCON_IO4 A4 8 EXPCON_IO5 E5 9 EXPCON_IO6 F6 10 EXPCON_IO7 C5 11 EXPCON_IO8 B2 12 EXPCON_IO9 A2 13 EXPCON_IO10 B3 14 EXPCON_IO11 A3 15 EXPCON_IO12 B4 16 EXPCON_IO13 D5 17 EXPCON_IO14 A5 18 EXPCON_IO15 B5 19 GND 20 EXPCON_3V3 21 EXPCON_IO16 A6 22 GND 23 EXPCON_IO17...

Страница 23: ...EF AREF PA03 L19 AR_AREF connection to AREF through R43 9 AR_SDA D20 PA22 SDA N18 Defaults to SDA function on Arduino ZERO Board It is optionally connected to SDA0 through R44 DNI 10 AR_SCL D21 PA23 SCL N19 Defaults to SCL function on Arduino ZERO Board It is optionally connected to SCL0 through R45 DNI Table 8 4 Arduino J3 Pin Connections J3 Pin Number Net Name Arduino ZERO Board Signal MachXO5 2...

Страница 24: ...D3 D17 ADC3 PA04 M14 Defaults to ADC3 on Arduino ZERO Board 5 AR_AD4 D18 ADC4 PA05 M17 Defaults to ADC4 on Arduino ZERO Board 6 AR_AD5 D19 ADC5 PB02 M18 Defaults to ADC5 on Arduino ZERO Board 8 3 FX12 Headers The board provides two headers U4 and U5 to connect to FX12 compatible boards or cables Each header has eight pairs of Low Voltage Differential Signaling LVDS signals for high speed data rece...

Страница 25: ...38 PWR_5 0V 39 SDA1 R4 40 SCL1 R5 Notes Signal is optionally connected to power source through resistor DNI 12 V power needs external supply from pin 8 of J4 Table 8 8 FX12 U5 Header Pin Connections U5 Pin Number Net Name MachXO5 25 Ball Location 1 CH1_DCK_P Y11 2 CH1_DCK_N W11 3 GND 4 CH1_DATA0_P V11 5 CH1_DATA0_N U11 6 GND 7 CH1_DATA2_P V12 8 CH1_DATA2_N U12 9 GND 10 FX_SN V3 11 FX_SCLK V4 12 PW...

Страница 26: ...USB It allows you to interface a Windows Linux or Mac OS X PC through USB to a downstream embedded system environment and transfer serial messages using the I2 C and SPI protocols The MachXO5 NX Development Board provides an Aardvark compatible header for customer applications The I2 C bus is optional connecting to a global I2 C bus on the board Table 8 9 Aardvark J7 Header Pin Connections J7 Pin ...

Страница 27: ...P_IO08 P2 25 GND 26 RASP_IO07 P1 27 RASP_ID_SD K2 28 RASP_ID_SC K1 29 RASP_IO05 N3 30 GND 31 RASP_IO06 N4 32 RASP_IO12 P3 33 RASP_IO13 P4 34 GND 35 RASP_IO19 P5 36 RASP_IO16 M5 37 RASP_IO26 P6 38 RASP_IO20 N7 39 GND 40 RASP_IO21 M8 Notes 3 3 V power is supplied from Raspberry Pi board 5 V power can come from either the Raspberry Pi board or the MachXO5 NX Development Board when jumper JP7 is insta...

Страница 28: ...nt Board support MIPI Camera sensor input with soft D PHY Figure 8 1 shows the block diagram of the MIPI Camera Sensor interface on the board The data path interface between the camera sensor module and MachXO5 25 is CSI 2 The cameras are configured from the MachXO5 25 device through the MIPI Sensor Control interface including I2 C frame sync and reset signals drive the camera MachXO5 NX U3 MIPI S...

Страница 29: ...GND 11 DPHY0_DN0 T13 12 DPHY0_DP0 U13 13 GND 14 DPHY0_DN2 U14 15 DPHY0_DP2 V13 16 GND 17 GND 18 VDD2V8 19 NC 20 DPHY0_CLK K7 21 DPHY0_FSYNC K6 22 DPHY0_SDA H5 23 DPHY0_SCL H6 24 DPHY0_RST H7 25 CVDD 26 VRAM DVDD1V8 27 GND 28 GND 29 AVDD2V8 30 GND Figure 8 2 MIPI Camera Sensor Power Supply Header 8 8 User I2 C Interface This board provides more options for user I2 C access from different MachXO5 25...

Страница 30: ...er I2 C control At this time JP12 and JP13 should be removed and R224 R225 or R226 R227 should be added to leverage the 1 8 V pull up for I O Bank 7 Table 8 14 I2 C Connections Extend header MachXO5 25 Bank MachXO5 25 Ball Location for JTAG Net Name Bridge Resistor to SCL0 SDA0 Versa Header J9 0 D5 EXPCON_IO13 R35 DNI B5 EXPCON_IO15 R37 DNI Aardvark Header J7 3 M19 AK_SCL R231 DNI M20 AK_SDA R230 ...

Страница 31: ... increase the voltage to ADCP1 rotate the POT counter clockwise Decreasing Wiper Voltage Wiper CW CCW Clockwise 1 2 3 Figure 8 5 Trimmer Wiper Description Optionally both ADC pairs are also routed to PMOD like header J28 For their signal assignment refer to Table 8 15 Table 8 15 J28 DNI Header Pin Connections J28 Pin Number Net Name MachXO5 25 Ball Location Application Notes 1 MDIR0 W1 Within IO B...

Страница 32: ...her brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice 32 FPGA EB 02052 1 0 8 10 Other Test Points The MachXO5 NX Development Board provides some test points for user flexibility Table 8 16 Test Point Connections Test Point Net Name MachXO5 25 Ball Location TP1 PMU_WAKEUPN G17 TP2...

Страница 33: ...nected to the four switches of SW1 as shown in the circuit design in Figure 9 1 The CTS side actuated DIP switches are connected to logic level 0 when in the ON position as shown in Figure 9 2 Figure 9 1 Four Position DIP Switch Circuits Figure 9 2 Four position DIP Switch One side of each switch is connected to GPIOs within the VCCIO5 bank and pulled up through 4 7 kΩ resistors The other side is ...

Страница 34: ...ect with EXPCON_IO20 which is connect to MANDATORY_RESET signal when mated with Lattice ASC Bridge Board Refer to ASC Bridge Board Evaluation Board User Guide FPGA EB 02025 for detailed information with ASC application SW5 can be used as PROGRAMN push button when JP5 is set to trigger the configuration process without power cycle For detailed information on PROGRAMN refer to MachXO5 Programming an...

Страница 35: ...legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA EB 02052 1 0 35 Table 9 4 Seven segment Display Connections Net Name D20 Pin Number MachXO5 25 Ball Location SEG_A 7 F14 SEG_B 6 G11 SEG_C 4 E15 SEG_D 2 F11 SEG_E 1 A15 SEG_F 9 A16 SEG_G 10 A17 SEG_DP 5 A18 ...

Страница 36: ...5 NX Development Board Radiant 3 11 or later version Radiant Programmer 3 11 or later version 11 Storage and Handling Static electricity can shorten the life span of electronic components Observe these tips to prevent damage that can occur from electrostatic discharge Use antistatic precautions such as operating on an antistatic mat and wearing an antistatic wristband Store the MachXO5 NX Developm...

Страница 37: ...laimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA EB 02052 1 0 37 Technical Support Assistance Submit a technical support case through www latticesemi com techsupport ...

Страница 38: ...6 Arduino Aardvark Headers BANK3 4 07 High Speed Headers BANK5 6 08 Raspberry Pi and LEDs BANK7 8 09 HyperRAM and ADC BANK9 10 POWER RAILS 11 POWER REGULATORS Date Size Schematic Rev o f Sheet Title Lattice Semiconductor Applications Email techsupport Latticesemi com Phone 503 268 8001 or 800 LATTICE Board Rev Project 1 0 MachXO5 NX Development Board A 1 11 Thursday January 13 2022 A Title Page Da...

Страница 39: ...IOs 1 8V 3 3V 24 IOs 1 2V 1 8V 24 IOs 1 2V 1 8V MIPI I F Control Pg7 Pg8 LEDs VCCIO0 2 U3 100mA 3 3V Prototype Area Pg6 50mA 1 8V 100mA 2 5V VCCIO3 U3 100mA 1 8V VCCIO7 U3 100mA 3 3V 100mA 3 3V 100mA 3 3V VCCIO8 U3 100mA 1 8V VCCIO9 U3 DC DC 1V U12 3 3V LDO U8 HyperRAM U6 U9 120mA 1 8V 100mA 1 0V SGMII PHY U7 90mA 2 5V 80mA 1 8V VCC_AUX VCC_AUXA VCC_AUXH VCC_ADC U3 2 5V LDO U13 FT2232 U1 300mA 3 3...

Страница 40: ...tor Applications Email techsupport Latticesemi com Phone 503 268 8001 or 800 LATTICE Board Rev Project 1 0 MachXO5 NX Development Board B 3 11 Thursday January 13 2022 A USB to Hard JTAG I F D9 Red C9 18pF R73 10K R6 0 R111 4 7k C12 100nF R48 4 7k R9 2 2K R162 0 R12 10K R19 12K Q1 MMBT3904 R125 1K R163 0 R23 0 C1 4 7uF 1 2 R26 2 2K L2 600ohm 500mA 1 2 R164 100K JP1 LS_DIS 1 2 R126 10K JP13 SDA 1 2...

Страница 41: ...Applications Email techsupport Latticesemi com Phone 503 268 8001 or 800 LATTICE Board Rev Project 1 0 MachXO5 NX Development Board B 4 10 Thursday January 13 2022 A USB to Soft JTAG I F BANK1 C140 100nF A B C D E F G DP D20 7 SEGMENT 7 6 4 2 1 9 10 5 3 8 R22 0 JP8 UFT_DIS 1 2 D12 ESDR0502N UDFN6 GND 1 NC2 2 NC3 3 D 4 VBUS 6 D 5 C129 4 7uF 1 2 R18 0 MachXO5 NX U3B VCCIO1 C12 VCCIO1 C14 VCCIO1 C17 ...

Страница 42: ... FTDI_SCL 3 FTDI_SDA 3 SCL0 3 6 8 9 SDA0 3 6 8 9 Date Size Schematic Rev o f Sheet Title Lattice Semiconductor Applications Email techsupport Latticesemi com Phone 503 268 8001 or 800 LATTICE Board Rev Project 1 0 MachXO5 NX Development Board B 5 11 Thursday January 13 2022 A Versa connector BANK0 2 Date Size Schematic Rev o f Sheet Title Lattice Semiconductor Applications Email techsupport Lattic...

Страница 43: ...i com Phone 503 268 8001 or 800 LATTICE Board Rev Project 1 0 MachXO5 NX Development Board B 6 11 Thursday January 13 2022 A Arduino Aardvark Headers BANK3 4 Date Size Schematic Rev o f Sheet Title Lattice Semiconductor Applications Email techsupport Latticesemi com Phone 503 268 8001 or 800 LATTICE Board Rev Project 1 0 MachXO5 NX Development Board B 6 11 Thursday January 13 2022 A Arduino Aardva...

Страница 44: ... Project 1 0 MachXO5 NX Development Board C 7 11 Thursday January 13 2022 A High Speed Heads BANK5 6 D13 Red R38 2 2K DNI C146 100nF C181 1uF R56 100 DNI C175 1uF C158 1uF R54 100 DNI R49 100 DNI C18 18pF C147 100nF R53 100 DNI MachXO5 NX U3F VCCIO5 T12 VCCIO5 V14 PB48B ADC_CN14 BDQ42 N12 PB48A ADC_CP14 BDQ42 N13 PB52A ADC_CP11 BDQ54 P13 PB40B COMP1IN PCLKC5_0 BDQ42 R11 PB52B ADC_CN11 BDQ54 R13 PB...

Страница 45: ...IR1 9 MDIR0 9 MEN0 9 MEN1 9 Date Size Schematic Rev o f Sheet Title Lattice Semiconductor Applications Email techsupport Latticesemi com Phone 503 268 8001 or 800 LATTICE Board Rev Project 1 0 MachXO5 NX Development Board B 8 11 Thursday January 13 2022 A Raspberry Pi and LEDs BANK7 8 Date Size Schematic Rev o f Sheet Title Lattice Semiconductor Applications Email techsupport Latticesemi com Phone...

Страница 46: ...Board Rev Project 1 0 MachXO5 NX Development Board B 9 11 Thursday January 13 2022 A HyperRAM and ADC BANK9 Date Size Schematic Rev o f Sheet Title Lattice Semiconductor Applications Email techsupport Latticesemi com Phone 503 268 8001 or 800 LATTICE Board Rev Project 1 0 MachXO5 NX Development Board B 9 11 Thursday January 13 2022 A HyperRAM and ADC BANK9 C34 100nF MachXO5 NX U3J VCCIO9 F2 VCCIO9...

Страница 47: ...ct 1 0 MachXO5 NX Development Board B 10 11 Thursday January 13 2022 A POWER RAILS Date Size Schematic Rev o f Sheet Title Lattice Semiconductor Applications Email techsupport Latticesemi com Phone 503 268 8001 or 800 LATTICE Board Rev Project 1 0 MachXO5 NX Development Board B 10 11 Thursday January 13 2022 A POWER RAILS TP16 1 JP26 VIO8 1 2 J25 VIOS 1 2 3 R132 1 J26 VS3 1 2 3 JP23 VIO5 1 2 J24 V...

Страница 48: ... 13 2022 A POWER REGULATORS Date Size Schematic Rev o f Sheet Title Lattice Semiconductor Applications Email techsupport Latticesemi com Phone 503 268 8001 or 800 LATTICE Board Rev Project 1 0 MachXO5 NX Development Board B 11 11 Thursday January 13 2022 A POWER REGULATORS C142 100nF C90 100nF C106 10uF R100 22k R101 4 7k R105 4 7k R99 124k C115 0 1nF C107 10uF C93 2 2uF C141 100nF C89 22uF SW6 2 ...

Страница 49: ...4 4 7uF C0603 885012106005 Wurth CAP CER 4 7UF 6 3V X5R 0603 3 C2 C4 C6 C7 C10 C11 C12 C13 C14 C17 C20 C21 C22 C23 C24 C25 C26 C27 C29 C30 C34 C62 C81 C85 C86 C87 C90 C92 C94 C96 C98 C99 C100 C101 C113 C114 C122 C123 C124 C125 C126 C127 C128 C131 C132 C133 C134 C135 C136 C140 C141 C142 C144 C145 C146 C147 C148 C149 C150 C151 C153 C155 62 100nF C0402 GRM155R71H1 04KE14D Murata CAP CER 0 1UF 50V X7R...

Страница 50: ...18 C158 C159 C160 C161 C167 C168 C173 C175 C179 C181 C185 13 1uF C0603 CL10A105KO8 NNNC Samsung CAP CER 1UF 16V X5R 0603 13 C119 C120 2 3 3nF C0201 GRM033R71A3 32JA01D Murata CAP CER 3300PF 10V X7R 0201 14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D13 D14 D15 12 Red led_0603 LTST C190KRKT LITE On INC LED RED CLEAR 0603 SMD 15 D10 D11 2 Green led_0603 LTST C190KGKT LITE On INC LED GREEN CLEAR CHIP SMD 16 D12 D19 ...

Страница 51: ... VERT 6POS 2 54MM DNI 26 J6 1 Receptac le 20X2 HDR254 2X20_soc ket PPTC202LFBN RC Sullins CONN HEADER FEM 40POS 1 DL TIN DNI 27 J7 1 HEADER 5X2 HDR254 2X5_SHR OUDED 30310 6002HB 3M CONN HEADER 10POS DL STR GOLD DNI 28 J8 J9 2 HDR40 HDR 20x2 PRPC020DFBN RC Sullins CONN HEADER VERT 40POS 2 54MM 29 J10 1 SMA bnc5 100 280t 5 1814832 1 TE Connectivity CONN SMA JACK STR 50 OHM PCB DNI 30 J11 J19 1 USB_M...

Страница 52: ... SPM6530 T 2R2M SPM6530T 1R5M100 TDK FIXED IND 1 5UH 11A 10 67MOHM SM 41 L10 1 SPM653 0T 3R3M SPM6530 T 2R2M SPM6530T 3R3M HZ TDK FIXED IND 3 3UH 6 8A 29 7MOHM SM 42 POT1 1 3314G 1 103E sot23 3314G 1 3314G 1 103E Bourns Inc TRIMMER 10K OHM 0 25W SMD 43 Q1 Q2 Q3 Q4 Q5 5 2N3904 MMBT390 4 MMBT3904 7 F Diodes TRANS NPN 40V 0 2A SOT 23 44 R1 R2 R3 R39 R40 R41 R42 R46 R47 R48 R101 R104 R105 R106 R111 R1...

Страница 53: ...52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 16 100 R0201 DNI 55 R65 R66 2 2 49K R0603 RT0603DRE072 K49L yageo RES SMD 2 49KOHM 0 5 1 10W 0603 56 R70 R71 R72 R109 R11 0 R144 R162 R163 R17 1 R223 10 0 R0402 AC0402JR 070RL yageo RES SMD 0 OHM JUMPER 1 16W 0402 57 R75 R183 R184 R185 R186 R187 R188 R189 R190 9 22 R0603 RC0603FR 0722RL yageo RES SMD 22 OHM 1 1 10W 0603 58 R80 R82 R113 R114 R115 R...

Страница 54: ...TP18 TP19 TP20 TP21 20 T POINT R TP DNI 70 U1 U18 2 FT2232H L tqfp64_0p 5_12p2x1 2p2_h1p6 FT2232HL TRAY FTDI IC USB HS DUAL UART FIFO 64 LQFP 71 U2 U19 2 93LC56C I SN so8_50_2 44 93LC56C I SN Microchip IC EEPROM 2KBIT 3MHZ 8SOIC 72 U3 1 JEDI_D6_ Final BGA400 080 17X17 SOCKET LFMXO5 25 9BBG400C Lattice Target Device 73 U4 U5 2 Hirose FX12 40 Pos Hirose FX12 FX12B 40P 0 4SV Hirose CONN PLUG 40POS 0 ...

Страница 55: ...iption Assembly 81 U15 1 RP115H1 81D SOT 89 5 SOT89 5 RP115H181D T1 FE RICOH IC REG LINEAR 1 8V 1A SOT89 5 82 U16 1 RP115H1 21D SOT 89 5 SOT89 5 RP115H121D T1 FE RICOH IC REG LINEAR 1 2V 1A SOT89 5 83 U20 1 RP111H2 81D SOT 89 5 SOT89 5 RP111H281D T1 FE RICOH IC REG LINEAR 2 8V 1A SOT89 5 84 X1 X2 2 7M 12 000M AAJ xtal_4p_7 m 7M 12 000MAAJ T TXC CRYSTAL 12MHZ 18PF SMD 85 X3 1 ABM3 25 XTAL_AB M3 ABM...

Страница 56: ...Connections ldc_set_location site T1 get_ports DIPSW 0 ldc_set_location site T2 get_ports DIPSW 1 ldc_set_location site T3 get_ports DIPSW 2 ldc_set_location site T4 get_ports DIPSW 3 Push Button Connections ldc_set_location site E19 get_ports PB1 ldc_set_location site F20 get_ports PB2 ldc_set_location site B7 get_ports PB3 ldc_set_location site G20 get_ports PB4 Clock inputs ldc_set_location sit...

Страница 57: ..._ports PMOD0_1 ldc_set_location site G9 get_ports PMOD0_2 ldc_set_location site G8 get_ports PMOD0_3 ldc_set_location site H8 get_ports PMOD0_4 ldc_set_location site F7 get_ports PMOD0_5 ldc_set_location site F9 get_ports PMOD0_6 ldc_set_location site F8 get_ports PMOD0_7 ldc_set_location site H9 get_ports PMOD0_8 PMOD1 Connections ldc_set_location site E11 get_ports PMOD1_1 ldc_set_location site ...

Страница 58: ...location site L4 get_ports RASP_IO27 ldc_set_location site K1 get_ports RASP_ID_SC ldc_set_location site K2 get_ports RASP_ID_SD VERSA HEADER Connections ldc_set_location site D3 get_ports EXPCON_IO0 ldc_set_location site E4 get_ports EXPCON_IO1 ldc_set_location site C3 get_ports EXPCON_IO2 ldc_set_location site C2 get_ports EXPCON_IO3 ldc_set_location site A4 get_ports EXPCON_IO4 ldc_set_location...

Страница 59: ...UT ldc_set_location site F5 get_ports HPE_RESOUT ldc_set_location site D8 get_ports HPE_CARDSEL Aardvark Header Connections ldc_set_location site M19 get_ports AK_SCL ldc_set_location site M20 get_ports AK_SDA ldc_set_location site N14 get_ports AK_MISO ldc_set_location site N15 get_ports AK_SCLK ldc_set_location site N16 get_ports AK_SS ldc_set_location site N17 get_ports AK_MOSI Arduino Header C...

Страница 60: ...ers The specifications and information herein are subject to change without notice 60 FPGA EB 02052 1 0 Appendix D MachXO5 NX Development Board Revision Information MachXO5 NX Development Board Working with Revision A BOM Difference of Revision A Board Feature Variations Without Ethernet With Ethernet Application Notes Major Identification J14 Top View U7 Bottom View BOM Difference J14 and U7 NOT ...

Страница 61: ...esemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA EB 02052 1 0 61 References For more information refer to the following documents MachXO5 Programming and Configuration User Guide FPGA TN 02271 Programming Cable User Guide FPGA UG 02042 ...

Страница 62: ... latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice 62 FPGA EB 02052 1 0 Revision History Revision 1 0 June 2022 Section Change Summary All Production release Revision 0 90 May 2022 Section Change Summary All Preliminary release ...

Страница 63: ...www latticesemi com ...

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