CrossLink Programming and Configuration Usage Guide
Technical Note
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FPGA-TN-02014-1.2
Use the following preferences to build a dual-boot design:
Table 5.3. Dual-Boot Configuration Settings
Preference
Dual-Boot Setting
MASTER_SPI_PORT
ENABLED
BOOT_UP_SEQUENCE
NVCM-EXT, EXT-NVCM, EXT-EXT
The failsafe configuration image generated by Diamond can be stored in either the NVCM or the external SPI Flash. In
dual boot scenarios where only one image is stored in the external SPI Flash (BOOT_UP_SEQUENCE = NVCM-EXT or
EXT-NVCM), the external image is stored in the SPI Flash starting at address 0x000000. This differs from a single image
Master SPI Configuration Mode (BOOT_UP_SEQUENCE = EXT-EXT), which requires the primary configuration data to be
stored at offset 0x000000 and the secondary configuration data at offset 0xFFFF00. The external SPI Flash memory file
for dual boot can be generated using the Diamond Deployment Tool. Use the External Memory: Dual Boot option in
Deployment Tool to generate the dual boot image.
The following processes are recommended for programming internal NVCM and external flash to use Dual Boot Mode:
Option A — Using background mode to program external flash:
1.
Program CrossLink internal NVCM (using NVCM Programming Mode). Make sure SPI port enabled and persistent is
on.
2.
Program the external SPI Flash.
3.
Refresh or power cycle.
Option B — Using offline mode to program external SPI Flash:
1.
Program the external SPI Flash first (may be none-background mode).
2.
Program CrossLink internal NVCM (using NVCM Programming Mode).
3.
Refresh or power cycle.
5.4.
Slave SPI Mode
CrossLink provides a Slave SPI (SSPI) configuration port that allows you to access features provided by the Configuration
Logic. You can program the NVCM and access status/control registers within the Configuration Logic block. It is
necessary to send a REFRESH command to load a new NVCM image into the SRAM.
To enter SSPI mode, CRESETB pin should be held LOW while an external SPI Master writes the Activation Key (
to the FPGA. During power up, the Activation Key must be written to CrossLink within 9.5 ms from V
CC
min while
CRESETB pin is held LOW.
Table 5.4. Slave SPI Port Pins
Pin Name
Description
SPI_SCK
Configuration clock input that is driven by a SPI master controller.
MOSI
Serial Data Input to the CrossLink Configuration Logic for command and data.
MISO
Serial Data Output from the CrossLink Configuration Logic.
SPI_SS
Chip select to enable the CrossLink Configuration Logic.
In the Slave SPI mode, the MLK/SPI_SCK pin becomes SPI_SCK (that is Configuration clock). Input data is read into the
CrossLink device on the MOSI pin at the rising edge of SPI_SCK. Output data is valid on the MISO pin at the falling edge
of SPI_SCK. The SPI_SS acts as the chip select signal. When SPI_SS is high, the SSPI interface is deselected and the MISO
pin is tri-stated.
Commands can be written into and data read from CrossLink when SPI_SS is asserted. The CrossLink SSPI port only
accepts Mode 0 bus transactions to the Configuration Logic, Where the Mode 0 bus transaction is the Master SPI
setting of configuration master configured at CPHA = 0 and CPOL = 0.
