CrossLink Programming and Configuration Usage Guide
Technical Note
© 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at
. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12
FPGA-TN-02014-1.2
DONE
CRESETB
t
PRGMJ
t
DPPDONE
Figure 4.3. Configuration from CRESETB Timing
DONE
PROGRAMN
Figure 4.4. Configuration Error Notification
If an error is detected when reading the bitstream, the internal DONE bit is not set, the CDONE pin stays LOW, and the
device does not wake up. The device configuration fails when the following occurs:
The bitstream CRC error is detected.
The invalid command error is detected.
A timeout error is encountered when loading from the on-chip Flash.
The program DONE command is not received when the end of on-chip SRAM configuration or on-chip NVCM is
reached.
Device ID code mismatch.
CDONE
The CDONE pin is a bi-directional open drain with a weak pull-up that signals the FPGA is in User mode. CDONE is first
able to indicate entry into User mode only after an internal DONE bit is asserted. The internal DONE bit defines the
beginning of the FPGA Wake-up state.
The CDONE output pin is controlled by the CDONE_PORT and DONE_EX configuration parameter that is modified in the
Diamond Spreadsheet View. By default, the CDONE pin is a general purpose I/O when CrossLink is in the Feature Row
HW Default Mode state. The default mode causes CrossLink to automatically pass through the Wake-up sequence after
the internal DONE bit is asserted. The FPGA does not stall waking up waiting for the CDONE pin to be asserted high.
The FPGA can be held from entering User Mode indefinitely by having an external agent keep the CDONE pin asserted
LOW. In order to use CDONE to stall entering User Mode, the CDONE_PORT must be set to CDONE_ONLY and the
DONE_EX set to ON, these setting are to be changed from Diamond Spread Sheet View. If DONE_EX = ON, the device
waits for CDONE to be driven high by an external signal to wake up. A common reason for keeping CDONE driven LOW
is to allow multiple FPGAs to be completely configured. As each FPGA reaches the DONE state, it is ready to begin
operation. The last FPGA to configure can cause all FPGAs to start in unison.
The CDONE pin drives LOW when the FPGA enters Initialization mode. As described earlier, this condition happens
when power is applied, CRESETB is asserted through HIGH to LOW transition or a Refresh command is received via an
active configuration port. Note that CRESETB is no longer level sensitive.
