Lakeshore 336, Руководство пользователя

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6.2.6 Status System Detail: Status Byte Register and Service Request 101
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6.2.6 Status System
Detail: Status Byte
Register and Service
Request As shown in FIGURE 6-1, the Status Byte Register receives the summary bits from the
two status register sets and the message available summary bit from the output
buffer. The status byte is used to generate a service request (SRQ). The selection of
summary bits that generates an SRQ is controlled by Service Request Enable Register.
6.2.6.1 Status Byte Register
The summary messages from the event registers and output buffer set or clear the
summary bits of the Status Byte Register (FIGURE 6-4). These summary bits are not
latched. Clearing an event register will clear the corresponding summary bit in the
Status Byte Register. Reading all messages in the output buffer, including any pending
queries, will clear the message available bit. The bits of the Status Byte Register are
described as follows:
D
Operation Summary (OSB), Bit (7): this bit is set when an enabled operation event
has occurred
D
Request Service (RQS)/Master Summary Status (MSS), Bit (6): this bit is set when a
summary bit and the summary bit’s corresponding enable bit in the Service
Request Enable Register are set. Once set, the user may read and clear the bit in
two different ways, which is why it is referred to as both the RQS and the MSS bit.
When this bit goes from low to high, the Service Request hardware line on the bus
is set; this is the RQS function of the bit (section 6.2.6.3). In addition, the status of
the bit may be read with the *STB? query, which returns the binary weighted sum
of all bits in the Status Byte; this is the MSS function of the bit.
Performing a serial poll will automatically clear the RQS function, but it will not clear
the MSS function. A *STB? will read the status of the MSS bit (along with all of the
summary bits), but also will not clear it. To clear the MSS bit, either clear the event
register that set the summary bit or disable the summary bit in the
Service Request Enable Register.
D
Event Summary (ESB), Bit (5): this bit is set when an enabled standard event has
occurred
D
Message Available (MAV), Bit (4): this bit is set when a message is available in the
output buffer
FIGURE 6-3 Operation event register
7 6 5 4 3 2 1
0
OR
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Operation
condition register
OPST?
Operation
event register
OPSTR?
Operation event
enable register
OPSTE, OPSTE?
CAL RAMP1 RAMP2 OVLD ALARM
CAL RAMP1 RAMP2 OVLD ALARM
CAL
COM
COM
COM RAMP1 RAMP2
ATUNE NRDG
ATUNE NRDG
ATUNE NRDG OVLD ALARM
– Decimal
– Name
– Bit
– Decimal
– Name
– Bit
– Decimal
– Name
– Bit
( OPSTR? reads and
clears the register)
To operation
event summary
bit (OSB) of
status byte
register
(see FIGURE 6-1)
8 4 2 1 16 32 64 128
8 4 2 1 16 32 64 128
8 4 2 1 16 32 64 128
AND
AND
AND
AND
AND
AND
AND
AND