3.3.8. Relative delays of the ADC, DAC and I/O channels.
Fig.3-4. Synchronous I/O diagram
In the above-mentioned synchronous I/O diagram, the output signal CONV_OUT is used as a
reference clock signal, with respect to which all I/O delays are described. Temporal parameters of the
diagram are described in the table below. The delays in the ADC channel are given for the operating
mode without averaging the data and without allocating additional cycles of the ADC for setting the
signal
Description
Desig-
nation
Timing sample
Minimum Typical
Maximum
Reference frequency period
t
REF
500 ns (2 MHz)
667 ns (1.5 MHz)
Duration of the signal pulse CONV_OUT
t
W
50 ns
Group delay time of analog channel of ADC
channel in E-502
t
ADC_SU
15-70 ns
The delay time from the front CONV_OUT
to the sampling time of the ADC chip
t
ADC
0 ns
The time to set the state "1" to
START_OUT before the front
CONV_OUT
(start of data collection)
t
ST_SU
45 ns
DAC1,
DAC2
CONV_OUT
START_OUT
DO
DI
1-
ый отсчёт
DO
2-
ый отсчёт
DO
Выборка
1-
го отсчёта АЦП
3-
ий отсчёт
DO
t
REF
2*t
REF
2*t
REF
Выборка
2-
го отсчёта АЦП
t
ADC
t
DI_SU
t
DI_H
Выборка
1-
го отсчёта
DI
Внутренний
преобразо
-
ватель
(
АЦП
)
Выборка
2-
го отсчёта
DI
1-
ый отсчёт
DAC1, DAC2
2-
ый отсчёт
DAC1, DAC2
3-
ий отсчёт
DAC1, DAC2
t
DO
t
DAC
Выборка
3-
го отсчёта АЦП
Выборка
3-
го отсчёта
DI
t
W
t
ST_SU
t
ST_H
X,Y,
GND32
t
ADC_SU
Sample
3rd ADC count
Sample
2nd ADC count
Sample
1st ADC count
Sample
3rd DI count
Sample
2nd DI count
Sample
1st DI count
1st DO count
2nd DO count
3rd DO count
3rd DAC1,
DAC2 count
1st DAC1, DAC2 count
2nd DAC1, DAC2 count
Internal
converter
(ADC)
