Kontron SMARC-sAL28, Руководство пользователя

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SMARC-sAL28 User Guide. Rev. 1.0
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Pin Signal Module
Direc-
tion Module
Termina-
tion Type/
Tolerance Connected Device Device pin name
S140 I2C_LCD_DAT Bi-Dir PU-2k21 CMOS 1.8V PTN3456I DDC_SDA
S141 LCD0_BKLT_PWM Out Serial-825R
PD-1k CMOS 1.8V PTN3460I/CPLD PWMO/ IO_L11
S142 RSVD - - 0.97V - 1.05V Tamper Power -
S143 GND - - GND GND GND
S144 EDP0_HPD - - CMOS 1.8V PTN3460I/
LS1028A HPDRX/ DP_HPD
S145 WDT_TIME_OUT# Out - CMOS 1.8V CPLD IO_D10
S146 PCIE_WAKE # In PU-4k75 CMOS 3.3V CPLD IO_F2
S147 VDD_RTC - Serial-1k PWR RTC power
S148 LID# In PU-4k75 CMOS 1.8V CPLD IO_D9
S149 SLEEP# In PU-4k75 CMOS 1.8V CPLD IO_B10
S150 VIN_PWR_BAD# In PU-10k CMOS VDDIN power circuit -
S151 CHARGING# In PU-CPLD CMOS 1.8V CPLD IO_C10
S152 CHARGER_PRSNT# In PU-CPLD CMOS 1.8V CPLD IO_F10
S153 CARRIER_STBY# Out Serial-825R
PD-1k CMOS 1.8V CPLD IO_L6
S154 CARRIER_PWR_ ON Out - CMOS 1.8V power circuit -
S155 FORCE_RECOV# In PU-4k75 CMOS 1.8V CPLD IO_B2
S156 BATLOW# In PU_CPLD CMOS 1.8V CPLD IO_G11
S157 TEST# In PU-10k CMOS 1.8V CPLD IO_B2
S158 GND - - GND GND GND
5.16. JTAG Debug connector
Table 23: JTAG Debug connector
Pin# Signal Description
1 JTAG_TCK JTAG clock
2 JTAG_TMS JTAG test mode select
3 PORESET# Power on reset for LS1028A,
low active signal ³
4 JTAG_TDO JTAG test data output
5 V_3V3_S0 3.3V supply and I/O level voltage
use also for JTAG_EN_3V3
6 JTAG_TDI JTAG test data input
7 JTAG_EN_3V3 JTAG enable,
high active signal
8 I2C_LOCAL_SDA_3V3 I2C_LOCAL bus data signal, I/O level: 3.3V
9 GND Ground
10 I2C_LOCAL_SCL_3V3 I2C_LOCAL bus clock signal, I/O level: 3.3V
³ need to be an open drain signal (push/pull with direct connection of CodeWarrior TAP would not work)