Kontron SMARC-sAL28, Руководство пользователя

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SMARC-sAL28 User Guide. Rev. 1.0
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5.4. I2C Buses
Four I2C buses are available at the
SMARC-sAL28 module.
Table 10: I2C Buses
SMARC
Connector I2C Bus LS1028A Devices with I2C address
-/- I2C_LOCAL IIC1 DP to LVDS converter PTN3460I (0x20)
USB HUB USB2517, (0x2c resistor option)
RTC RV8803 (0x32)
CPLD (0x4a)
RCW EEPROM AT24C32 (0x50)
I2C_PM I2C_PM IIC4
1
No devices at module connected
I2C_GP I2C_GP IIC5 Module EEPROM AT24C32 (0x50)
I2C_LCD I2C_LCD² -/- No devices at module connected
1 Shares second CAN bus, therefore options to short PM bus with I2C local or I2C GP bus are available
² The I2C bus for LCD display (I2C_LCD_SDA, I2C_LCD_SCL) derived from the DP-to-LVDS display converter and is
only available with the LVDS display converter option
The SMB_ALERT_1V8# signal derives from CPLD (register 0x1C, bit 1).
5.5. SPI Interfaces
Two SPI buses are available at the
SMARC-sAL28 module.
Table 11: SPI Buses
SMARC
Connector LS1028A
SPI0 SPI3
ESPI XSPI1_A
SPI0 in standard option has one chip select (SPI0_CS0#). Optional the second chip (SPI0_CS1#) select is possible
with abandonment of USB3 power control from CPU.
ESPI in standard option has SPI flash on board at the first chip select. The second chip select is available at the
SMARC connector (ESPI_CS1#). Optional, the first chip select (ESPI_CS0#) is reconfigurable from SPI flash to the
SMARC connector.
The ESPI signals ESPI_ALERT0#, ESPI_ALERT1# and ESPI_RESET# derive from CPLD:
ESPI_ALERT0#: CPLD register 0x1C, bit 2
ESPI_ALERT1#: CPLD register 0x1C, bit 3
5.6. eMMC NAND Flash Memory
The SDHC2 interface of the LS1028A is connected to the eMMC.
Specific eMMC Flash memory features are:
 Up to 64 GByte pSLC (or 128 GB MLC)
 eMMC 5.1 specification
 Class 0 (basic); class 2 (block read); class 4 (block write); class 5 (erase); class 6 (write protection); class 7 (lock
card)
 HS200 modes
 DDR modes up to 52 MHz clock speed
 ECC and block management