SMARC-sAL28 User Guide. Rev. 1.0
// 20
3.3.
Functional Block Diagram
The block diagram shows all available interfaces on the sAL28 module.
Figure 2: Block Diagram
Clock generator
SAIx
DDR3L
memory down
5 x8 devices
SMARC 2.0 pinout connector
NXP LS1028A
DDR3L
memory down
5 devices x8
x36
USB[1] 3.0 OTG
USB[2] 2.0
eMMC
WIBU
Key
1G
PHY
PCIe 3.0/SATA Lane D
PCIe
A
PCIe
B
PCIe
C
eSDHS
2
eSDHC
1
SDIO Card
x4
1588
/GPIO
/
RGMII
/SAI
Display port 1.3 and eDP 1.4
LVDS
0
/e
DP
eDP to
LVDS
x8
GBE
0
DDR3 + ECC
SPI
[3
] (
CS
0#
)
SPI
0
XSPI
1_
A CS
0#
eSPI
/SPI
1
SER
[1
],SER
[3
]
DUART
[1
:2
]
FLEXCAN
[1
]
CAN
[0
]
I2
C_
LCD
I2
C_
GP
I2
C_
PM
I2C[4] / FLEXCAN[2]
RCW
0x
50
EEPROM
RTC
TAMPER
Standard
component
Connector
Option
LVDS
1
PCIe
D
SATA
PCIe 3.0/10G-SXGMII/SGMII Lane A
PCIe 3.0/QSGMII/SGMII Lane B
PCIe 3.0/SGMII Lane C
SPI N
OR
boot flash
CS#
MDC
/MDIO
I2
S0
USB
0
USB
1
USB
2
USB
3
USB
5
USB
4
USB HUB
USB
0
USB
1
USB
2
USB
3
USB
4
DP
1G
PHY
GBE
1
GPIOs
Power
USB
5
USB
-up
0R
VDD
_IN
_5
V0
VDD
_RTC
_3
V0
TD
1
(The
rmal Diode
)
SD1_REF_CLK2
SD1_REF_CLK1
100MHz w/ SSC
125MHz/
156.25MHz
w/o SSC
SYSCLK
100MHz w/o SSC
BOOT
_SEL
SYSTEM
CPLD
GPIOs
cfg[3:0]
3
JTAG
JTAG chain
GP
0x
50
EEPROM
DP_REF_CLK
27MHz w/o SSC
SER
[0
]
LPUART
[2
]
USB
6
0R
RSVD
0R
0R
CAN
[1
]
XSPI
1_
A and CS
1#
I2
C_
LOCAL
0R
0R
0R
I2C[5]
PCIE_A_CLK 100MHz w/o SSC
PCIE_B_CLK 100MHz w/o SSC
PCIE_C_CLK 100MHz w/o SSC
USB hub 24MHz
JTAG header
TAG connect
JTAG chain
JTAG chain
JTAG chain
I2
C_
LOCAL
V2.02
0R
0R
I2C[1]
0R
Содержание SMARC-sAL28
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