Configuration
EBC2
Page 4 - 8
© 2005 Kontron Modular Computers GmbH
ID 29022, Rev. 01
26873
.02.VC.050120/135455
P R E L I M I N A R Y
4.5
EBC2 Register Description
The following sections provide register descriptions for the:
• Digital Input Data Register
• Digital Output Data Register
• POST Code Data Register
4.5.1
Digital Input Data Register
The digital input data register indicates the status of the respective input signals.
Address Offset:
0x0000 0000
Format:
Byte
Access:
Read
Value after reset:
0x00 (if inputs are left open)
Digital input channels 0 to 3 are active, channels 4 to 7 are not used.
Table 4-4: Digital Input Data Register
REGISTER NAME
Digital Input Data Register
ACCESS
ADDRESS
0x0000 0000 (offset)
R
BIT POSITION
MSB
7
6
5
4
3
2
1
0
LS
B
CONTENT
DIN_
DATA_7
DIN_
DATA_6
DIN_
DATA_5
DIN_
DATA_4
DIN_
DATA_3
DIN_
DATA_2
DIN_
DATA_1
DIN_
DATA_0
DEFAULT
0
0
0
0
0
0
0
0
0
DIN_
DATA_0
0
Input signal is low or open
1
Input signal is high
1
DIN_
DATA_1
0
Input signal is low or open
1
Input signal is high
2
DIN_
DATA_2
0
Input signal is low or open
1
Input signal is high
3
DIN_
DATA_3
0
Input signal is low or open
1
Input signal is high
4
DIN_
DATA_4
0
Channel not used
1
5
DIN_
DATA_5
0
Channel not used
1
6
DIN_
DATA_6
0
Channel not used
1
7
DIN_
DATA_7
0
Channel not used
1