Kontron CP690HS, Руководство пользователя

Страница: 59 / 84

CP690HS Hot Swap
ID 20955, Rev. 05 Page 5 - 9
P R E L I M I N A R Y
5.2.6.2 GPIO Input Data Register - Offset 67h
This section describes the GPIO input data register.
Dword address = 64h
Byte enable p_cbe_1<3:0> = 0xxxb
Table 5-3: GPIO Output Enable Control Register - Offset 66h
Dword BIT NAME R/W DESCRIPTION
19:16 GPIO output
enable
write-1-to-clear R/W1TC The gpio<3:0> output enable control
write-1-to-clear. Writing 1 to any of these bits configures the cor-
responding gpio<3:0> pin as an input only; that is, the output
driver is tristated.
Writing 0 to this register has no effect.
When read, reflects the last value written.
Reset value: 0 (all pins are input only).
23:20 GPIO output
enable
write-1-to-set R/W1TS The gpio<3:0> output enable control
write-1-to-set. Writing 1 to any of these bits configures the cor-
responding gpio<3:0> pin as bidirectional, that is,
enables the output driver and drives the value set in the output
data register (65h).
Writing 0 to this register has no effect.
When read, reflects the last value written.
Reset value: 0 (all pins are input only).
Table 5-4: GPIO Input Data Register - Offset 67h
Dword BIT NAME R/W DESCRIPTION
27:24 Reserved R Reserved. Returns 0 when read.
31:28 GPIO input R This read-only register reads the state of the gpio<3:0> pins.
This state is updated on the
PCI clock cycle following a change in the gpio pins.