Kontron CP690HS, Руководство пользователя

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CP690HS Functional Description
ID 20955, Rev. 05 Page 2 - 7
P R E L I M I N A R Y
2.1.2 CompactPCI Bus Connector
Figure 2-2: CompactPCI Connectors J1, J2, J3, and J5
The CompactPCI interface provides all the necessary signals for data trans-
fer as defined by the PCI Specification Rev. 2.1.
The CP690HS is connected to the CompactPCI backplane using the Pericom
PI7C8154B PCI-to-PCI bridge, which interfaces the board with a data path width
of 32 or 64-bit and a speed up to 33/66MHz. All bus signals are provided on the
CompactPCI connectors J1 and J2 (64-bit extension). In addition to meeting the re-
quirements of the interface definition of the CompactPCI Specification PICMG 2.0
R2.1, the CP690HS is designed to comply with the CompactPCI Hot Swap speci-
fication PICMG 2.1 R1.0, a consequence of which is that the CompactPCI inter-
face of the board will be precharged when the board is plugged into a running
system.
The complete CompactPCI connector configuration comprises four connec-
tors named J1, J2, J3, and J5. Their functions are as follows:
• J1 and J2: 32/64-bit CompactPCI interface with PCI bus signals, arbi-
tration, clock and power
• J3 and J5 have rear I/O interface functionality from the PMC module
The CP690HS is designed for a CompactPCI bus architecture. The CompactPCI
standard is electrically identical to the PCI local bus. However, these systems are
enhanced to operate in rugged industrial environments and to support multiple
slots.
2.1.2.1 CompactPCI Connector Keying
The CompactPCI connectors support guide lugs to ensure a correct polarized
mating.
The CP690HS supports universal CompactPCI VI/O signaling voltages with
one common termination resistor configuration and includes a CompactPCI
VI/O voltage detection circuit. If the CompactPCI VI/O voltage is 5 V, the max-
imum supported CompactPCI frequency is 33 MHz.
2.1.2.2 Hot Swap Support
To ensure that a board may be removed and replaced in a working bus with-
out disturbing the system, the following additional features are required:
• Power ramping
• Precharge
• Hot swap control and status register bits
• Automatic interrupt generation whenever a board is about to be re-
moved or replaced
• An LED to indicate that the board may be safely removed
For further information regarding the hot swap capability of the CP690HS, re-
fer to Chapter 5.2, “Design Implementation on CP690HS”.
Note:
Pinrows F and Z
are GND pins.
25
A E C
D B Z F
1
22
1
J1
J2
22
1
J5
19
1
J3