Kontron CP3005-SA, Руководство пользователя

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CP3005-SA – Rev. 0.6 Preliminary
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4.3.7. Board Interrupt Configuration Register (BICFG)
The Board Interrupt Configuration Register holds a series of bits defining the interrupt routing.
Table 19: Board Interrupt Configuration Register (BICFG)
Address 0x286
Bit 7 6 5 4 3 2 1 0
Name UICF CFICF CEICF CDICF
Reserved
R
00
WICF
R/W
00
Access R/W R/W R/W R/W
Reset 1 0 0 0
Bitfield Description
7 UICF UART IRQ3 and IRQ4 interrupt configuration:
0 = IRQ3 and IRQ4 interrupt disabled
1 = IRQ3 and IRQ4 interrupt enabled
6 CFICF CPCI fail signal interrupt configuration (FAL signal):
0 = IRQ5 disabled
1 = IRQ5 enabled
5 CEICF CPCI enumeration signal interrupt configuration (ENUM signal):
0 = IRQ5 disabled
1 = IRQ5 enabled
4 CDICF CPCI derate signal interrupt configuration (DEG signal):
0 = IRQ5 disabled
1 = IRQ5 enabled
1 - 0 WICF Watchdog interrupt configuration:
00 = Disabled
01 = IRQ5
10 = Reserved
11 = Reserved
4.3.8. Status Register 2 (STAT2)
The Status Register 2 holds status information related to the rear I/O configuration.
Table 20: Status Register 2 (STAT2)
Address 0x287
Bit 7 6 5 4 3 2 1 0
Name
Reserved
R
00
RCFG
R
N/A*
MEZC
R
N/A*
Access
Reset
Bitfield Description
5 - 4 RCFG Rear I/O configuration:
00 = Rear I/O disabled (CP3005-SA front I/O version)
01 = COMA, GPIO
10 = Reserved