Configuration
AM4100
Page 4 - 4
ID 36126, Rev. 2.0
P R E L I M I N A R Y
4.1.1.1
POST Code or User-Specific LED Configuration
The User-Specific LEDs are available for either general application use or for indicating the
POST code value in the POST Code Register.
The default setting is indicated by using italic bold.
4.1.1.2
NetBootLoader Firmware Flash Configuration
For the NetBootLoader (NBL) Firmware there are two redundant NOR Flash chips on the
AM4100 board. One chip is intended to provide a backup in the event that the other gets cor-
rupted. If the currently used NetBootLoader Flash is corrupted due to physical damage or a
faulty Flash upgrade, either the Module Management Controller or the SW2 DIP switch can se-
lect the redundant Flash, and the system can boot from it.
Switch 2 provides a hardware toggle function to force the onboard logic to switch from the cur-
rently used Flash to the redundant Flash. For example, if the switch is in the OFF position,
switching to the ON position will force the use of the redundant Flash during the next boot op-
eration.
4.1.1.3
Core 1 LM Address Offset Mode Configuration
Switch 4 controls the optional hardware Low-Memory Address Offset Mode for the e600 core 1.
For further information on the Low Memory Address Offset Mode, refer to the respective section
in the current Freescale’s MPC8641D Integrated Host Processor Family Reference Manual.
The default setting is indicated by using italic bold.
Table 4-2:
POST Code or User-Specific LED Configuration
SWITCH 1
DESCRIPTION
OFF
Enable POST Code configuration (User -Specific LED configuration disabled)
ON
Enable User-Specific LED configuration (POST Code configuration disabled)
Table 4-3:
NetBootLoader Firmware Flash Configuration
SWITCH 2
DESCRIPTION
OFF
Toggle to the currently redundant NBL Firmware Flash when switching from ON to OFF.
ON
Toggle to the currently redundant NBL Firmware Flash when switching from OFF to ON.
Table 4-4:
Core 1 Low Memory Address Offset Mode
SWITCH 4
DESCRIPTION
OFF
Core 1 LM Address Offset Mode disabled (SMP)
ON
Core 1 LM Address Offset Mode enabled (AMP)
Содержание AM4100
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