6.2 Dedicated I/O
AKD Firmware
AKD Connector AKD Pin
Name
SynqNet MPI
Name
Notes
DIN1.STATE
X7-10
Digital Input 1
Dedicated input
"HOME"
High speed opto
input. Also maps to
DIN 1 (HS).
DIN5.STATE
X8-6
Digital Input 5
Dedicated input
"LIMIT_HW_POS"
Also maps to "DIN
5."
DIN6.STATE
X8-5
Digital Input 6
Dedicated input
"LIMIT_HW_NEG"
Also maps to "DIN
6."
DIN11.STATE
X9-7/8
Emulated
Encoder Zero
Dedicated input
"INDEX_
SECONDARY"
Also maps to
"RS485 IO 3."
NA
X10-6/7
Zero
Dedicated input
"INDEX_
PRIMARY"
Also maps to "Ana-
log Z Pulse." Some
encoder types do
not use index pin.
NA
X8-1/2
Fault Relay Out-
put
Dedicated input
"AMP_FAULT"
Logical OR of AKD
and SynqNet faults
FB1.HALLSTATEU
X10-1
Hall U
Dedicated input
"Hall A"
See note on bit
order
FB1.HALLSTATEV
X10-2
Hall V
Dedicated input
"Hall B"
See note on bit
order
FB1.HALLSTATEW
X10-3
Hall W
Dedicated input
"Hall C"
See note on bit
order
MOTOR.BRAKESTATE
Dedicated output
"BRAKE_
RELEASE"
Dedicated input
"BRAKE_
APPLIED"
Brake release is
command from Syn-
qNet Brake applied
is status from AKD
drive (logical OR)
Notes:
l
Hall input bit order is swapped in beta release FPGAs. Planned (corrected) order shown above.
l
For AKD FPGA versions 0200 and prior, AKD U/V/W maps to Hall C/B/A.
l
For AKD FPGA versions TBD and later, AKD U/V/W maps to Hall A/B/C.
l
GPIO input "Analog Z Pulse" not supported on AKD Rev 7 control boards (AKD-SQ prototypes only).
6.3 Node I/O
AKD Firmware
AKD Connector
AKD Pin Name
SynqNet MPI Name
AOUT.VALUE
X8-7/8
Analog Output
Nodelo AnalogOut[0] output
AIN.VALUE
X8-10/9
Analog Input
Nodelo AnalogIn[0] input
AKD SynqNet | 6 AKD SynqNet I/O Mapping
Kollmorgen | kdn.kollmorgen.com | October 2020
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