Keysight Technologies D9020DDRC, Руководство пользователя

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17 Command and Address Timing (CAT) Tests
320 DDR2(+LP) Compliance Testing Methods of Implementation
tIPW, Address and Control Input Pulse Width - Test Method of Implementation
The purpose of this test is to verify that the width of the high or low level of address or control or
command/address signal must be within the conformance limit as specified in the JEDEC
specification.
Signals of Interest
Mode Supported: DDR2. LPDDR2
Signal cycle of interest: WRITE
Require Read/Write separation: No
Signal(s) of Interest:
• Address Signal (DDR2 only) OR Command/Address Signal (LPDDR2 only) OR Control Signal
Signals required to perform the test on the oscilloscope:
• Address Signal (DDR2 only) OR Command/Address Signal (LPDDR2 only) OR Control Signal
Test Definition Notes from the Specification
Table 228 Timing Parameters by Speed Grade (DDR2-400 and DDR2-533) & (DDR2-667 and DDR2-800)
Parameter Symbol DDR2-400 DDR2-533 Units Specific Notes
Min Max Min Max
Control & Address input pulse width for
each input tIPW 0.6 x 0.6 x tCK
Parameter Symbol DDR2-667 DDR2-800 Units
34
Specific
Notes
Min Max Min Max
Control & Address input pulse width for
each input tIPW 0.6 x 0.6 x tCK(avg)
Table 229 Timing Parameters by Speed Grade (DDR2-1066)
Parameter Symbol DDR2-1066 Units
29
Specific Notes
Min Max
Control & Address input pulse width for
each input tIPW 0.6 x tCK(avg)
Table 230 LPDDR2 AC Timing Table
Parameter Symbol Min
Max Min
t
CK
LPDDR2 Unit
1066 933 800 677 533 466*
5
400 333 266*
5
200*
5
Command Address Input Parameters*
14
Address and
control input
pulse width
tIPW Min
0.40 t
CK(avg)