Keysight Technologies AC6801B, Руководство по эксплуатации и обслуживанию

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Status Byte Register
This register summarizes the information from all other status groups and stores STB and RQS
messages as defined by the IEEE 488 standard. The *STB? query reads the status byte register and
transmits the contents of the status byte register and the master status summary (MSS) message.
The *STB? query does not change the status byte, MSS, or RQS.
Bit Value Bit Name Description
0 1 Reserved Reserved for future use; always set to 0.
1 2 Reserved Reserved for future use; always set to 0.
2 4 Error/Event Queue
(EEQ) One or more errors are in the error queue. Use SYSTem:ERRor? to read and delete errors.
3 8 Questionable
Status Summary
(QUES) One or more bits are set in the Questionable Data Register and the corresponding QUEStionable
status enable register bit is true. See STATus:QUEStionable:ENABle.
4 16 Message Available
(MAV) Data is available in the instrument's output buffer.
5 32 Event Status Sum-
mary (ESB) One or more bits are set in the Standard Event Status Register. Bits must be enabled, see *ESE .
6 64 Request Service
(RQS/MSS) One or more bits are set in the Status Byte Register and may generate a Request for Service or
the Master Summary Status has one or more event bits. Bits must be enabled, see
*SRE .
7 128 Operation Status
Summary (OPER) An event in the Operation Status register has been generated. Bits must be enabled, see
STATus:OPERation:ENABle .
Master Status Summary and Request for Service Bits
MSS is a real-time (unlatched) summary of all Status Byte register bits that are enabled by the Service
Request Enable register. MSS is set when the instrument has one or more reasons for requesting
service. *STB? reads the MSS in bit position 6 of the response but does not clear any bits in the Status
Byte register.
The RQS bit is a latched version of the MSS bit. Whenever the instrument requests service, it sets the
SRQ interrupt line true and latches RQS into bit 6 of the Status Byte register. When the controller does
a serial poll, RQS is cleared inside the register and returned in bit position 6 of the response. Other
Status Byte register bits are not disturbed.
Error and Output Queues
The Error Queue is a first-in, first-out (FIFO) data register that stores numerical and textual description
of an error or event. Error messages are stored until they are read with SYSTem:ERRor? If the queue
overflows, the last error/event in the queue is replaced with error -350,"Queue overflow".
The Output Queue is a first-in, first-out (FIFO) data register that stores instrument-to-controller
messages until the controller reads them. Whenever the queue holds messages, it sets the MAV bit
(4) of the Status Byte register.
Keysight AC6800B Series Operating and Service Guide 105
3 SCPI Programming Reference