RD-DV5-S/DV7-L/DV5MD-S
19
CIRCUIT DESCRIPTION
✽
MN677521HB X35-229, IC300 DV-5900M/DVF-R9050
✽
MN677533MP X35-230, IC301 DV-5050M/DVF-J6050 RMD-SJ5, RD-DV5/7
Port No.
Port Name
I/O
Function
94,95
TESTSEL1,0
-
Connected to digital ground.
97~102,106,108
TEST4~TEST9
109
TEST3,1,0
O
Unused.
103
CLKMON
O
Unused.
107
RFF
O
Unused.
110
IECOUT
O
IEC958 format data output.
111
DMIX
O
Audio down mix signal output.
Over sampling DAC clock output.
fs= 48kHz: 384fs= 18.432MHz output
fs= 96kHz: 384fs= 36.864MHz output
113
DACCK
O
fs= 192kHz: 192fs= 36.864MHz output
fs= 44.1kHz: 384fs= 16.9344MHz output
fs= 88.2kHz: 384fs= 33.8688MHz output
fs= 176.4kHz: 192fs= 33.8688MHz output
114
LRCK
O
LR clock output.
115
SRCK
O
Bit clock output.
117~119
ADOUT(0~2)
O
Audio data output (0~2).
121
XPOWD
I
DAC power down control input.
122
VREFC
I
DAC reference voltage input for C signal.
123
IREFC
I
DAC bias current setting port for C signal.
124
COMPC
I
Capacitance connection for DAC (C signal) stabilization.
125
VCOUT
O
Unused.
126,136
AVDD
-
Analog supply voltage (+3.3V) for DAC.
127
VREFCB
I
DAC reference voltage input for CB signal.
128
IREFCB
I
DAC bias current setting port for CB signal.
129
COMPCB
I
Capacitance connection for DAC (CB signal) stabilization.
130
VCBOUT
O
Unused.
131,141
AVSS
-
Analog ground for DAC.
132
VREFCR
I
DAC reference voltage input for CR signal.
133
IREFCR
I
DAC bias current setting port for CR signal.
134
COMPCR
I
Capacitance connection for DAC (CR signal) stabilization.
135
VCROUT
O
Unused.
137
VREFY
I
DAC reference voltage input for Y signal.
138
IREFY
I
DAC bias current setting port for Y signal.
139
COMPY
I
Capacitance connection for DAC (Y signal) stabilization.
140
VYOUT
O
Unused.
143
XYSYNCO
I/O
Vertical synchronizing signal input/output.
144
XHSYNCO
I/O
Horizontal synchronizing signal input/output.
146
VCLK
O
Clock output for digital video data output.
148~155
VD0~VD7
O
Digital video data output (0~7).
158,159,161,162,164
165,167,168,170,171
MDQ0~MDQ15
I/O
SDRAM data bus (0~15).
173,175,177,178,180
181
183
MCKI
I
Clock input from SDRAM.
185
MCK
O
Clock output to SDRAM.
187
DQMLE
O
Lower bite data, mask signal of expander SDRAM.
189
DQMLM
O
Lower bite data, mask signal of main SDRAM.
190
DQMUE
O
Upper bite data, mask signal of expander SDRAM.
192
DQMUM
O
Upper bite data, mask signal of main SDRAM.
193
XWE
O
Write enable signal of SDRAM.
195
XCAS
O
CAS signal of SDRAM.
196
XRAS
O
RAS signal of SDRAM.
198
XCSE
O
Chip select signal of expander SDARM.
199
XCSM
O
Chip select signal of main SDARM.