DV-605/DVF-R5060-S
6
CIRCUIT DESCRIPTION
Pin No.
Pin Name
I/O
Pin Description
80
SMI DQMU
O
DQ MASK enable up.
82
SMI CLKIN
I
SDRAM clock input.
84~93
SMI DATA(0~9)
I/O SDRAM data bus.
95
SMI CLKOUT
O
SDRAM clock out.
97~102
SDI DATA(10~15)
I/O SDRAM data bus.
Reserved
103
ADC SCLK
I/O Digital audio port clock (Unused).
104
ADC LRCLK
I/O ADC sample rate clock (Unused).
105
ADC DATA
I
ADC digital audio data input (Unused).
106
ADC PCMCLK
O
Crystal input or master clock input (Unused).
JTAG
109
TRST
I
Test reset from emulator module.
110
TMS
I
Test mode select.
111
TDO
O
Test data out to emulator module.
112
TDI
I
Test data input from emulator module.
113
TCK
I
Test clock input from emulator module.
Timers
114
PWM2
I/O Unused.
115
PWM1
I/O ROM boot option port (voltage low = emulator booting).
116
PWM0
I/O Unused.
EMI Interface
117
CPU OE
I/O Flash ROM output enable.
118
CPU PRO CLK
O
SDRAM clock (unused).
Clock & Reset
120
PIX CLK
I
27MHz main clock input.
122
VDD PLL
-
Supply voltage for PLL (+2V5).
123
VSS PLL
-
Ground for PLL.
124
RESET
I
Chip reset input.
Interrupt
125
IRQ(2)
I
Interrupt request 2 from front-end module.
126
IRQ(1)
I
Unused.
127
IRQ(0)
I
Unused.
EMI Interface
128
CPU BE(0)
O
BYTE0 Enable
129
CPU BE(1)
O
BYTE1 Enable
130
CPU RW
O
Unused.
131
CPU WAIT
I
Wait state (connected to ground)
132
CPU CE(3)
O
Chip select bank 3
133
CPU CE(2)
O
Chip select bank 2
134
CPU CE(1)
O
Unused.
135
CPU CE(0)
O
Unused.
138
CPU RAS1
I/O Unused.
139
CPU CAS0
O
Unused.
140
CPU CAS1
O
Unused.
141~148
CPU DATA(0~7)
I/O Flash ROM data input/output (0~7).
151~158
CPU DATA(8~15)
I/O Flash ROM data input/output (8~15).
161~170
CPU ADR(1~10)
O
Flash ROM address (1~10).
173~183
CPU ADR(11~21)
O
Flash ROM address (11~21).
PIOs and communication
186
PIO0(0) T STROBE
I/O UART0 Data
187
PIO0(1) MOD SW
I/O ATAPI RD
188
PIO0(2) VFD STB
O
VFD strobe output.
189
PIO0(3) VFD CLK
O
VFD clock output.
190
PIO0(4) VFD DATA OUT
O
VFD data output.
191
PIO0(5) VFD DATA IN
I
Data input from VFD.
